ECE 352 Week 7

For a sequential circuit with n inputs and m states, the minimum number of state transitions that could enter a given state could be

0

How to create a Mealy diagram

1. Draw circles for all the different states from the state table (distinct values of Q) 2. Draw transition lines between states. Include A/Y, where A is the input and Y is the output for each row of the truth table. ** Note that Y is the output of the circuit while the circuit is in the state the arrow is leaving while the given input A is present.

How to create a Moore diagram

1. Draw circles for all the different states from the state table (distinct values of Q). 2. Draw lines that represent the transitions for each row of the truth table. 3. Add output values for each state to the bottom of the state circle.

Using a state table to design a sequential circuit

1. Fill in the desired circuit behavior in the state table for each current state/input combination. 2. Create minimized logic equations for next state (FF inputs) and circuit output. Use a K-Map to do this. The inputs for the two equations are Q and A.

Using a state table to analyze a sequential circuit

1. Write a state table with all possible combinations of current state and input 2. Examine the diagram to write equations for the next state and output. Then fill in the state table. 3. Examine the state table to see what the circuit does.

For a sequential circuit with n inputs and m states, the minimum number of state transitions that could exit a given state could be

2^n. Consider the state table. There must be a possible next state for all valid input at each state.

Before a flip flop is reset or has an active clock edge, it contains:

A 0 or a 1.

"Transparent" Latch

A D-Latch is transparent since while the clock signal is high, the output of the D-Latch will continuously change to match the input (Q output is equal to D input). This will occur for any level-sensitive elements.

Level-Sensitive Latch

A D-Latch that has its enable connected to the clock. It will take a value when control = 1. This is opposed to edge-sensitive like a D-FF.

State diagram

A graphical depiction of the state table. Circles represent the states in the diagram. In an FSM circuit with N flip-flops, the state is encoded as an N-bit binary number. N bits can represent up to 2^N states.

Finite state machine (FSM)

A sequential circuit that has a finite number of possible states. The number of states is limited by the number of flip-flops in the circuit. It is usually used to describe a device that performs a task (e.g. a memory device wouldn't usually be described as a FSM, although it is). All practical sequential circuits are FSMs.

Each line of the state table corresponds to:

A transition

Asynchronous Sequential circuits

A transition to the next state can be taken as soon as it is determined. These aren't used in ECE 352.

D- Latch "Inverter Loop"

A value will stay present in the loop as long as the circuit has power

D Flip Flop positive edge triggered

Add an inverter to the clock on the negative edge triggered D Flip Flop.

Asynchronous input

Affects the Flip-Flop immediately without requiring an active clock edge.

D- Latch with control implementation

An inverter loop connected to a tristate. The bottom inverter is weak and the tristate buffer can overpower it without damage. Other implementations are also possible.

In a functional waveform, the time delay is:

Assumed to be zero.

D Flip-Flop, negative edge sensitive

Build a "Flip Flop" (FF) by connecting two latches together in a master-slave organization. The output of the flip flop changes on the negative edge of the clock.

Legend on state diagram

Details input and output signals. E.g. Input A, Output Y.

State transitions are represented by:

Directed lines. Arrows indicate the direction of the transition. It is labeled with the input values that cause the transition.

2 Bit saturating up/down counter

Does not overflow past 0 or 3. Instead, it stays put if told to go "further".

During a clock cycle, Mealy machines outputs can ________ the transition arrows during a clock cycle. Only the input value at the active clock edge determines which transition is taken.

During a clock cycle, Mealy machines outputs can "jump between" the transition arrows during a clock cycle. Only the input value at the active clock edge determines which transition is taken.

FSM counters

FSM counters are one of the simplest sequential circuits. It counts through a predetermined sequence of values. The current state is the circuit output. It may also have an enable. If enabled, the circuit moves to the next value at the positive clock edge. It may also have an up/down. It can count different sequences.

When completing the waveform of a sequential circuit, you should always figure out what first

First figure out Q (current state), since the next state and output will depend on it.

Unless specified otherwise, you are to assume that all waveforms are:

Functional (i.e. there are no delays)

Synchronous input

Has no effect unless the clock is at an active edge.

Why aren't D-Latches used alone?

If a D-Latch is used along, the value will change the entire time Control (C) is 1 and not just at the rising edge, since a D-Latch is "transparent"

Flip Flops and Timing Waveforms

In reality, there is some delay after the active clock edge before the FF input is stored and appears at the FF output. Timing waveforms show this delay.

If the data input to a D-FF changes from 0 to 1 at the same time that the FF is triggered by a clock edge, the FF output Q will be:

Indeterminate. The same is true if the data input changes from 1 to 0. This rarely occurs in practice, however. This would only really be clearly shown on a timing waveform. This would usually only occur if the input changes at the positive edge of the clock.

When can Moore Machine outputs change? When can Mealy Machine outputs change?

Moore Machine outputs can only change at positive clock edges (since that's when the state can change) while Mealy Machine output can change between positive clock edges (since the input can change).

How are circuit outputs shown on a state diagram

Moore Machine: Inside the state circle Mealy Machine: On the transitions.

Can you make an asynchronous D-Flip Flop reset without modifying the internals of the D-Flip flop (i.e. from the outside)?

No. You need to implement this internally.

Sequential circuits

Outputs are a function of not only the current circuit inputs but also previous inputs. You can also think of sequential circuits as blocks of combinational logic separated by flip-flops.

Clock signal

Special signal that oscillates between 0 and 1 at a specific frequency. It controls how often storage elements can update.

Synchronous sequential circuits

Storage elements hold the current state. The circuit's activity is governed by the clock. The clock is connected directly to the flip flops. Don't add any logic to the clock signal. Once per clock cycle, the values are updates (next becomes current).

FF Direct inputs in Quartus

The FF in Quartus have active low preset (PRN) and clear (CLRN) inputs. PRN = 0 forces the FF to immediately store a 1. CLRN = 0 forces the FF to immediately store a 0. **You must tie these to 1 if unused.

Moore Machine

The circuit's output equation is based exclusively on the FF outputs.

Mealy machine

The circuit's output equation is based on FF outputs and circuit inputs.

Input forming logic (IFL)

The equations for the next state. This is implemented as combinational logic that feeds the FF inputs (D).

Flip-Flops and functional waveforms

The functional waveform doesn't show delay, but it must still express causality. Thus, the next value (Q) is what was on D before the active edge.

State of a sequential circuit

The set of values stored in its flip flops. It is a code of 1s and 0s that represents everything "important" that happened since the circuit was reset.

Current state

The set of values that are stored in the FFs at a given time (Q).

Next state

The set of values that will be stored into the FFs when they change state. Thus, the next state is the inputs to the FFs that have not yet been stored into the FFs (D).

State table

The state table lists the next state and current output values for all possible current state and circuit input values. It is essentially two truth tables in one that shows all possible combinations of current state and circuit inputs and the resulting next state and circuit outputs. The columns are Q, A, D, and Y.

Reset Symbol on state diagram

The state the machine will start in. Shown with a curvy arrow.

PRE and CLR/RESET direct inputs on FF

They can be used to force a circuit to a known state on start-up. PRE (Preset): forces FF to 1 CLR (Clear) aka RESET: forces FF to 0.

Glitches

When short pulses are the unintended result of unequal delay paths within a combinational circuit.

D-Latch with Q output tied to D input

Will oscillate between 0 and 1 when enable is 1 and hold at an unknown value when enable is zero.

For a two-variable K-Map, "Kitty Corners" or "checkerboard" may result in a

XOR or XNOR