EECS 140 Review

Using comparator in Module 58, slide 6: What is AgtB?

!(AeqB + AltB)

Using comparator in Module 58, slide 6: What is AeqB?

!(AltB + AgtB)

What is the decimal value of the following 2's complement numbers: 10 1110 0111 01 1101 1110 11 1111 1110

-281 478 -2

Referring to a 2n-to-n binary encoder in Figure 6.22 (Module 56, Slide 2). Given: 6-to-3 encoder Assume: w5 = 0, w4 = 0, w3 = 0, w2 = 0, w1 = 0, and w0 = 1 Then: y2 = , y1 = , y0 =

0 0 0

Using the truth table for the 4-to-2 priority encoder in Figure 6.24, Module 57, slide 3 as a model: Note: Slide 3 in the video incorrectly says it is a 4-to-1 priority encoder, but the PowerPoint in the BlackBoard Lesson is correct. Given: 3-to-2 priority encoder Assume: z = 0, y1 = 0, and y0 = 1 Then: w2 = , w1 = , w0 =

0 0 0

Referring to a n-to-2n binary decoder in Figure 6.15 (Module 55, Slide 2): Assume: En = 0 w2 = 1, w1 = 1, and w0 = 1 Then: y0 = , y1 = , y2 = , y3 = , y4 = , y5 = , y6 = , and y7 =

0 0 0 0 0 0 0

Referring to a n-to-2n binary decoder in Figure 6.15 (Module 55, Slide 2): Assume: En = 0, w2 = 1, w1 = 0, and w0 = 1 Then: y0 = , y1 = , y2 = , y3 = , y4 = , y5 = , y6 = , and y7 =

0 0 0 0 0 0 0

Referring to a 2n-to-n binary encoder in Figure 6.22 (Module 56, Slide 2). Given: 6-to-3 encoder Assume: y2 = 1, y1 = 0, y0 = 1

1 0 0 0 0 0

What is the decimal number 10 in unsigned binary?

1010

It is estimated that there are between 1078 to 1082 atoms in the known universe. Which IEEE floating point format could we use to represent this number? Either single or double precision. Neither one. The number is too small. Single precision Double precision Neither one. The number is too large.

Double precision

From the list below fill in the steps for converting an AND-OR circuit to one with all NOR gates: Step 1: Step 2: Step 3: Step 4: A. Use DeMorgan's theorem to convert AND gates to NOR gates. B. Use DeMorgan's theorem to convert OR gates to NAND gates. C. Use double inversion to invert inputs of AND gates D. Use double inversion to invert inputs of OR gates E. Use double inversion to invert outputs of AND gates F. Use double inversion to invert outputs of OR gates G. Use NAND gates to realize necessary inversions. H. Use NOR gates to realize necessary inversions.

F, C, A, H

Given the function: g(a,b,c) = bc + ac + ab Using Shannon's Expansion Theorem, what is (are) the cofactor(s) of g with respect to c? (Do not reduce the cofactors).

a b ab

Using Shannon's Expansion Theorem, what is (are) the cofactor(s) of g with respect to !a? (Do not reduce the cofactors).

bc

As we add more bits, the logic to generate the lookahead carry in a non-hierarchical carry-lookahead adder becomes more complicated because we () the fan-in of the () gate and add an () gate with () fan-in for each bit added.

increase xor and idk

Design a 3-to-2 encoder with 3 inputs: w2, w1, and w0 (no subscripts) and 2 outputs: y1 and y0. What are the logical equations for y1 and y0? Enter your answers in alphabetic order with no blanks. y1 = y0 =

w2 w1

Let X = 5 and Y = -2 Give the inputs and outputs of a 4-bit adder/subtractor unit as depicted in Figure 5.13 (Module 40 - Slide 4), to calculate X - Y. x3 = ; x2 = ; x1 = ; x0 = y3 = ; y2 = ; y1 = ; y0 = !Add/Sub =, s3 = ; s2 = ; s1 = ; s0 = cn =

x3 = 0; x2 = 1; x1 = 0; x0 =1 y3 =1 ; y2 = 1; y1 = 1; y0 =0 !Add/Sub =,1 s3 =0 ; s2 = 1; s1 = 1; s0 =1 cn =0

Referring to the D flip-flops with Clear and Preset in Figure 7.13 and Slide 2 of Module 66, fill-in the following table: ClkDPresetClearQ!Q0010[Q1][NQ1]0101[Q2][NQ2]1010[Q3][NQ3]1101[Q4][NQ4] Referring to Figure 7.14(c) and Slide 3 of Module 66, fill-in the following truth table for the logic to add a synchronous clear and preset to a flip-flop, where the inputs are D, Clear, and Preset and the output is the D input to the flip-flop (DFF). Assume when both Clear and Preset are 0, DFF = D. DClearPresetDFF000[DFF0]001[DFF1]010[DFF2]011[DFF3]100[DFF4]101[DFF5]110[DFF6]111[DFF7]

0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 1

Using the truth table for the 4-to-2 priority encoder in Figure 6.24, Module 57, slide 3 as a model: Note: Slide 3 in the video incorrectly says it is a 4-to-1 priority encoder, but the PowerPoint in the BlackBoard Lesson is correct. Given: 3-to-2 priority encoder Assume: w2 = 1 w1 = 0, and w0 = 1 Then: y1 = , y0 = , z =

1 0 1

Referring to a n-to-2n binary decoder in Figure 6.15 (Module 55, Slide 2): Assume: y0 = 0, y1 = 0, y2 = 0, y3 = 1, y4 = 0, y5 = 0, y6 = 0, and y7 = 0 Then: En = , w2 = , w1 = , and w0 = (Use d for don't care)

1 0 1 1

Referring to Figure 6.3 (Slide 14, Module 49). Assume the values for of s1 and s0 are 00, 01, 10, 11, 00, 01, 10, and 11 at times t0, t1, t2, t3, t4, t5, t6, and t7, respectively. Assume the values of w0, w2, and w3 are a constant 1 and the the value of w1 is a constant 0. What is the value of f at time t0? What is the value of f at time t1? What is the value of f at time t2? What is the value of f at time t3? What is the value of f at time t4? What is the value of f at time t5? What is the value of f at time t6? What is the value of f at time t7?

1 0 1 1 1 0 1 1

Referring to a n-to-2n binary decoder in Figure 6.15 (Module 55, Slide 2): Assume: y0 = 0, y1 = 0, y2 = 0, y3 = 0, y4 = 0, y5 = 1, y6 = 0, and y7 = 0 Then: En = , w2 = , w1 = , and w0 = (Use d for don't care)

1 1 0 1

QUESTION 5 Referring to a n-to-2n binary decoder in Figure 6.15 (Module 55, Slide 2): Assume: y0 = 0, y1 = 0, y2 = 0, y3 = 0, y4 = 0, y5 = 0, y6 = 1, and y7 = 0 Then: En = , w2 = , w1 = , and w0 = (Use d for don't care)

1 1 1 0

Referring to the LUT in Slide 9 of Module 51. What values, from top to bottom, are the blue boxes set to, to implement f(x1,x2) = !(x1x2)?

1 1 1 0

Referring to the array multiplier for unsigned numbers in Figure 5.32 (Slide 5, Module 45): The gate delay to generate m1 and q1 is . The gate delay to generate the carry-out in each full-adder (FA) is . The critical path in a 4-bit array multiplier is full-adders. The total gate delay for a 4-bit array multiplier is gates. If the gate delay is 1/17 ns, how many multiplications can a 4-bit array adder perform per second? Enter your answer is an integer with no commas.

1 2 8 17 1 billion

Using comparator for signed numbers in Figure 5.43, Module 59, slide 2-4: If X = 1001 and Y = 0111, the outputs of the comparator are: V = ; N = ; Z =

1 0 0

Using comparator for signed numbers in Figure 5.43, Module 59, slide 2-4: Fill-in the following truth table where Z, V, and N are inputs and XgeY is the output: Hint: There are 3 "don't care" (d) values. ZVNXgeY000001010011100101110111

1 0 0 1 1 d d d

Using comparator for signed numbers in Figure 5.43, Module 59, slide 2-4: If X = 0111 and Y = 1001, the outputs of the comparator are: V = ; N = ; Z =

1 1 0

Express the following decimal numbers in binary form: 17 = 8.5 = 9.75 = 73.03125 = 67.375 =

1) 10001 2) 1000.1 3) 1001.11 4) 1001001.00001 5) 1000011.011

Convert the following binary numbers to decimal. 101.101 = 111.11 = 1010.01 = 111.111 = 1000.0101 = 10101.011 =

1) 5.625 2) 7.75 3) 10.25 4) 7.875 5) 8.3125 6) 21.375

We are going to use two 8-to-1 multiplexers to implement the full-adder (FA) depicted in Figure 5.4 (Module 35, Slide 7). The selectors for the multiplexers, s2, s1, and s0 will be connected to ci, xi, and yi, respectively. For the mux that produces ci+1, values for: w0 = , w1 = , w2 = , w3 = , w4 = , w5 = , w6 = , and w7 = . For the mux that produces si, values for: w0 = , w1 = , w2 = , w3 = , w4 = , w5 = , w6 = , and w7 = .

0 0 0 1 0 1 1 1 0 1 1 0 1 0 0 1

f we want to perform the function f(A,B), then TopS1 = , TopS0 = , BottomS1 = , and BottomS0 = . If we want to perform the function f(C,A), then TopS1 = , TopS0 = , BottomS1 = , and BottomS0 = . If we want to perform the function f(B,D), then TopS1 = , TopS0= , BottomS1 = , and BottomS0 = .

0 0 0 1 1 0 0 0 0 1 1 1

Referring to the LUT in Slide 9 of Module 51. What values, from top to bottom, are the blue boxes set to, to implement f(x1,x2) = XOR(x1,x2)?

0 1 1 0

Referring to the LUT in Slide 9 of Module 51. What values, from top to bottom, are the blue boxes set to, to implement f(x1,x2) = x1+x2?

0 1 1 1

Using the truth table for the 4-to-2 priority encoder in Figure 6.24, Module 57, slide 3 as a model: Note: Slide 3 in the video incorrectly says it is a 4-to-1 priority encoder, but the PowerPoint in the BlackBoard Lesson is correct. Given: 3-to-2 priority encoder Assume: z = 1, y1 = 0, and y0 = 1 Then: w2 = , w1 = , w0 =

0 1 z

Referring to a n-to-2n binary decoder in Figure 6.15 (Module 55, Slide 2): Assume: y0 = 0, y1 = 0, y2 = 0, y3 = 0, y4 = 0, y5 = 0, y6 = 0, and y7 = 0 Then: En = , w2 = , w1 = , and w0 = (Use d for don't care)

0 d d d

Referring to the shift register in Figure 7.18 and Slide 3 Module 68, fill in the following table: InQ1Q2Q3Q4 = Outt000000t11t20t31t40t51t60t70 If the first bit out is the least-significant-bit and the last bit out is the most-significant-bit, the output of the shift register for t1-t7 =

0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1010000

Using comparator for signed numbers in Figure 5.43, Module 59, slide 2-4: If X = 0010 and Y = 0010, the outputs of the comparator are: V = ; N = ; Z =

0 0 1

Referring to the gated SR latch designed with NAND gates as depicted in Figure 7.7 and Slide 4 of Module 61: Fill in the following table: TimeClkSRQ!Qt1101t2010t3001t4000t5110t6101t7100 What is the gate delay for the gated SR latch? The cost of the gated SR latch = gates + inputs =

0 1 0 1 0 1 1 0 0 1 0 1 3 4 8 12

Referring to the basic SR latch constructed with NAND gates as depicted in Slide 6 of Module 60, fill-in the following table: TimeSRQaQbt101[Qa1][Qb1]t200[Qa2][Qb2]t310[Qa3][Qb3]t400[Qa4][Qb4]t500[Qa5][Qb5]

0 1 0 1 1 0 1 0 1 0

Referring to the basic SR latch constructed with NOR gates as depicted in Figure 7.5(a) and Slide 4 of Module 60, fill-in the following table: TimeSRQaQbt101[Qa1][Qb1]t200[Qa2][Qb2]t310[Qa3][Qb3]t400[Qa4][Qb4]t500[Qa5][Qb5]

0 1 0 1 1 0 1 0 1 0

What is hexadecimal AA in binary?

10101010

What is the binary number 1011 in decimal?

11

Add these 12-bit 2's complement numbers. Give your answer as signed decimal numbers: 00110110 - 00101011 = 11010011 - 11101100 =

11 -25

What is octal 16 in binary?

1110

What is the decimal number 15 in binary?

1111

What is hexadecimal 1F in binary?

11111

What is the 12-bit 2's complement representation of these decimal numbers (enter the answer with no spaces)? -95 -1630 73 1906

111110100001 100110100010 000001001001 011101110010

If the propagation delay through a full-adder (FA) is 150 nsec, what is the total propagation delay in nsec of an 8-bit adder?

1200

Add these 12-bit 2's complement numbers. Give your answer as signed decimal numbers: 00110110 + 01000101 = 01110101 + 11011110 = 11011111 + 10111000 =

123 83 -105

What is the binary number 1110 in decimal?

14

What is binary 1101 in octal?

15

Let X = 7 and Y = 2. Suppose we want to add X - Y using 2s complement arithmetic. Give the inputs and outputs of a 4-bit adder/subtractor unit that detects overflow as depicted below: x3 = ; x2 = ; x1 = ; x0 = y3 = ; y2 = ; y1 = ; y0 = !Add/Sub = s3 = ; s2 = ; s1 = ; s0 = cn = Overflow =

x3 = 0; x2 = 1; x1 = 1; x0 =1 y3 = 0; y2 = 0; y1 = 1; y0 =0 !Add/Sub =1 s3 =0 ; s2 =1 ; s1 =0 ; s0 =1 cn =1 Overflow =0

Let X = 5 and Y = -2 Give the inputs and outputs of a 4-bit adder/subtractor unit as depicted in Figure 5.13 (Module 40 - Slide 4), to calculate X + Y.

x3 = 0; x2 =1 ; x1 =0 ; x0 =1 y3 =1 ; y2 =1 ; y1 =1 ; y0 =0 !Add/Sub =0 s3 =0 ; s2 = 0; s1 = 1; s0 =1 cn =1

Let X = 7 and Y = 2. Suppose we want to add X + Y using 2s complement arithmetic. Give the inputs and outputs of a 4-bit adder/subtractor unit that detects overflow as depicted below: x3 = ; x2 = ; x1 = ; x0 = y3 = ; y2 = ; y1 = ; y0 = !Add/Sub = s3 = ; s2 = ; s1 = ; s0 = cn = Overflow =

x3 =.0 ; x2 = 1; x1 =1 ; x0 =1 y3 = 0; y2 =0 ; y1 =1 ; y0 =0 !Add/Sub =0 s3 =1 ; s2 =0 ; s1 =0 ; s0 =1 cn =0 Overflow =1

nmos closed

x=0

nmos open

x=1

What is the sum function or s(x,y) for a half-adder (HA)? |+| = XOR c_in = carry-in c_out = carry-out

x[+]y

What is the sum function or s(x,y,c_in) for a full-adder (FA)? |+| = XOR c_in = carry-in c_out = carry-out

x[+]y{+}c_in

What is the carry function or c(x,y) for a half-adder (HA)? |+| = XOR c_in = carry-in c_out = carry-out

xy

What is the carry-out function or c(x,y,c_in) for a full-adder (FA)? |+| = XOR c_in = carry-in c_out = carry-out

xy+xc_in+yc_in

Given: x = bit of number we want to add y = bit of number we want to add to x cin = carry-in to addition of x and y cout = carry-out of addition of x and y s = sum of x and y plus any carry-in. The SOP for cout = (from Module 35). The gate delay for this function is . Factoring out cin gives us cout = . The gate delay for this function is . Letting g = xy and p = x+y, we can functionally decompose cout = . The gate delay for this function is . Slide 5 of Module 43 shows expanding this concept to the i+1 carry-out. The gate delay for ci+1 as depicted on Slide 5 is . Using this carry-lookahead formula, the gate delay for calculating the carry-out of a 4-bit adder is . Using this formula, the gate delay for calculating the carry-in to the last stage of a 4-bit adder is . Recalling from Module 35, s is the XOR of , , and . The gate delay for calculating s from the last stage of a 4-bit adder is . The gate delay for a 4-bit carry-lookahead adder is . The gate delay for an 8-bit carry-lookahead adder is .

xy+xcin+ycin 2 xy+(x+y)cin 3 g+pcin 2 3 3 3 x,y,cin 1 4 4

What is the binary number 101 in decimal?

5

Given the function: g(a,b,c) = bc + ac + ab Using Shannon's Expansion Theorem, what is (are) the cofactor(s) of g with respect to !c? (Do not reduce the cofactors).

ab

Given the function: g(a,b,c) = bc + ac + ab Using Shannon's Expansion Theorem, what is (are) the cofactor(s) of g with respect to !b? (Do not reduce the cofactors).

ac

Given the function: g(a,b,c) = bc + ac + ab Using Shannon's Expansion Theorem, what is (are) the cofactor(s) of g with respect to a? (Do not reduce the cofactors).

b c bc

Given the function: g(a,b,c) = bc + ac + ab Using Shannon's Expansion Theorem, what is (are) the cofactor(s) of g with respect to b? (Do not reduce the cofactors).

c a ac

Given: X = 1101 where X is represented by the bits x3, x2, x1, and x0, with x3 being the most significant bit and x0 being the least significant bit. Y = 1001 where Y is represented by the bits y3, y2, y1, and y0, with y3 being the most significant bit and y0 being the least significant bit. 4-bit ripple-carry adder with c0 set to 0. If we add X and Y with the ripple-carry adder, what are the output values of:

c4= 1, s3=0, s2=1, s1=1, s0=0

Referring to Slide 2, Module 42: The - is the longest sequence of gates. The - is the propagation delay through the -. The -determines how fast a logic circuit performs an operation.

critical-path critical-path delay, longest sequence of gates critical-path delay

What is binary 1101 in hexadecimal?

d

Using the truth table for the 4-to-2 priority encoder in Figure 6.24, Module 57, slide 3 as a model: Note: Slide 3 in the video incorrectly says it is a 4-to-1 priority encoder, but the PowerPoint in the BlackBoard Lesson is correct. Given: 3-to-2 priority encoder Assume: w2 = 0, w1 = 0, and w0 = 0 Then: y1 = , y0 = , z =

d d x

What is the advantage of a hierarchical carry-lookahead adder? It has a shorter gate delay than a non-hierarchical carry-lookahead adder and therefore is faster than a non-hierarchical carry-lookahead adder. It reduces the fan-in problem of a non-hierarchical carry-lookahead adder. It increases fan-in, which reduces the gate delay and makes it faster than a non-hierarchical carry-lookahead adder. None of these are advantages of a hierarchical carry-lookahead adder.

It reduces the fan-in problem of a non-hierarchical carry-lookahead adder.

Using the truth table for the 4-to-2 priority encoder in Figure 6.24, Module 57, slide 3 as a model: Note: Slide 3 in the video incorrectly says it is a 4-to-1 priority encoder, but the PowerPoint in the BlackBoard Lesson is correct. Fill-in the following truth table for the 3-to-2 priority encoder.

d d 0 0 0 1 0 0 1 1 1 1

Referring to a n-to-2n binary decoder in Figure 6.15 (Module 55, Slide 2): Assume: En = 1, w2 = 0, w1 = 1, and w0 = 1 Then: y0 = , y1 = , y2 = , y3 = , y4 = , y5 = , y6 = , and y7 =

0 0 0 1 0 0 0

QUESTION 4 Referring to a n-to-2n binary decoder in Figure 6.15 (Module 55, Slide 2): Assume: En = 1, w2 = 1, w1 = 1, and w0 = 1 Then: y0 = , y1 = , y2 = , y3 = , y4 = , y5 = , y6 = , and y7 =

0 0 0 0 0 0 1

Referring to a 2n-to-n binary encoder in Figure 6.22 (Module 56, Slide 2). Given: 6-to-3 encoder Assume: y2 = 0, y1 = 0, y0 = 0

0 0 0 0 0 1

Referring to the LUT in Slide 9 of Module 51. What values, from top to bottom, are the blue boxes set to, to implement f(x1,x2) = x1x2?

0 0 0 1

QUESTION 1 Referring to the T flip-flop in Figure 7.16 and Slide 2 of Module 67, fill-in the following table: Q(t)TQ(t+1)!Q(t+1)00011011 30 points QUESTION 2 Referring to the JK flip-flop in Figure 7.17 and Slide 3 of Module 67, fill-in the following table: Q(t)JKQ(t+1)!Q(t+1)000001010011100101110111 59 points QUESTION 3 Select the following statements about gated latches and flip-flops that are true. Outputs of positive-edge-triggered flip-flops change when the clock is 1. Outputs of negative-edge-triggered flip-flops change when the clock changes from 0 to 1. Outputs of positive-edge-triggered flip-flops change when the clock is 0. Outputs of positive-edge-triggered flip-flops change when the clock changes from 0 to 1. Outputs of positive-edge-triggered flip-flops change when the clock changes from 1 to 0. Outputs of negative-edge-triggered flip-flops change when the clock changes from 1 to 0. Outputs of gated latches change when the clock is 0. Outputs of negative-edge-triggered flip-flops change when the clock is 0. Outputs of negative-edge-triggered flip-flops changed when the clock is 1. Outputs of gated latches change when the clock is 1.

0 1 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 0 0 1 1 0 0 1 positive edge-triggered flip flop work when the clock changes from 0 to 1. Negative edge-triggered flip flop work when the clock changes from 1to 0. Outputs of gated latches change when the clock is 1.

Referring to the gated D latch as depicted in Figure 7.8(a) and Slide 2 of Module 62: Fill in the following table: TimeClkDQ!Qt110[Q1][NQ1]t211[Q2][NQ2]t300[Q3][NQ3]t401[Q4][NQ4] What is the gate delay for the gated D latch? [D] The cost of the gated D latch = [G] gates + [I] inputs = [C]

0 1 1 0 1 0 1 0 4 5 9 14

QUESTION 1 Referring to the positive-edge triggered D flip-flop as depicted in Figure 7.11 and Slide 3 of Module 64: Let ↓ represent a negative-edge and ↑ represent a positive-edge. Fill in the following table: TimeClkDQ!Qt1↑0t2↑1t310t411t5↓0t6↓1t700t801 The cost of the positive-edge triggered D flip-flop = gates + inputs =

0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 6 13 19

Referring to the negative-edge triggered D flip-flop designed with NOR gates as depicted in Slide 3 of Module 65: Let ↓ represent a negative-edge and ↑ represent a positive-edge. Fill in the following table: TimeClkDQ!Qt1↓0[Q1][NQ1]t2↓1[Q2][NQ2]t300[Q3][NQ3]t401[Q4][NQ4]t5↑0[Q5][NQ5]t6↑1[Q6][NQ6]t710[Q7][NQ7]t811[Q8][NQ8] The cost of this negative-edge triggered D flip-flop = [G] gates + [I] inputs = [C] Is this more, less, or the same as the cost of the negative-edge triggered D flip-flop designed with gated D latches in Module 63? [A] Is this more, less, or the same as the cost of the positive-edge triggered D flip-flop designed with NAND gates in Module 64? [B]

0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 6 13 19 less same

Referring to the master-slave D flip-flop as depicted in Figure 7.10 and Slide 4 of Module 63: Let ↓ represent a negative-edge. Fill in the following table: TimeClkDQ!Qt1↓0[Q1][NQ1]t2↓1[Q2][NQ2]t300[Q3][NQ3]t401[Q4][NQ4]t510[Q5][NQ5]t611[Q6][NQ6] Referring to the gated D latch as depicted in Figure 7.8(a) and Slide 2 of Module 62: The cost of the master-slave D flip-flop = [G] gates + [I] inputs = [C]

0 1 1 0 1 0 1 0 1 0 1 0 11 19 30

Using comparator for signed numbers in Figure 5.43, Module 59, slide 2-4: If X = 0010 and Y = 0011, the outputs of the comparator are: V = ; N = ; Z =

0 1 0

Using comparator for signed numbers in Figure 5.43, Module 59, slide 2-4: If X = 1001 and Y = 0000, the outputs of the comparator are: V = ; N = ; Z =

0 1 0

Using comparator in Figure 6.26, Module 58, slide 5, fill-in the following outputs for the given inputs: a3a2a1a0b3b2b1b0AeqBAltBAgtB00000001[1][2][3]01000100[4][5][6]00010000[7][8][9]10000111[10][11][12]01111000[13][14][15]

0 1 0 1 0 0 0 0 1 0 1 0

Using comparator in Module 58, slide 6: If A = 0001 and B = 0001, what are the outputs? AgtB = [1]; AgeB = [2]; AeqB = [3]; AleB = [4]; AltB = [5] If A = 0010 and B = 0001, what are the outputs? AgtB = [6]; AgeB = [7]; AeqB = [8]; AleB = [9]; AltB = [10] If A = 0010 and B = 0011, what are the outputs? AgtB = [11]; AgeB = [12]; AeqB = [13]; AleB = [14]; AltB = [15]

0 1 1 1 1 0 1 1 0 0 0 0 0 0 1 1

Convert these numbers to 4-bit 2's complement and add them. Give your answer as 4-bit 2's complement numbers: 5 - 2 = -5 - 2 = 5 - (-2) = -5 - (-2) =

0011 1001 0111 1101

A 3-bit full-adder is used add the binary numbers 101 and 101. The 3-bit sum from the full-adder is: The carry-out from the full-adder is:

010, 1

Convert these numbers to 4-bit 2's complement and add them. Give your answer as 4-bit 2's complement numbers: 5 + 2 = 5 + (-2) = -5 + 2 = -5 + (-2) =

0111 0011 1101 1001

Referring to a 2n-to-n binary encoder in Figure 6.22 (Module 56, Slide 2). Given: 6-to-3 encoder Assume: w5 = 0, w4 = 1, w3 = 0, w2 = 0, w1 = 0, and w0 = 0 Then: y2 = , y1 = , y0 =

1 0 0

QUESTION 3 Referring to a n-to-2n binary decoder in Figure 6.15 (Module 55, Slide 2): Assume: y0 = 1, y1 = 0, y2 = 0, y3 = 0, y4 = 0, y5 = 0, y6 = 0, and y7 = 0 Then: En = , w2 = , w1 = , and w0 = (Use d for don't care)

1 0 0 0

Referring to the LUT in Slide 9 of Module 51. What values, from top to bottom, are the blue boxes set to, to implement f(x1,x2) = !(x1+x2)?

1 0 0 0

Referring to a n-to-2n binary decoder in Figure 6.15 (Module 55, Slide 2): Assume: En = 1, w2 = 0, w1 = 0, and w0 = 0 Then: y0 = , y1 = , y2 = , y3 = , y4 = , y5 = , y6 = , and y7 =

1 0 0 0 0 0 0

Referring to the hierarchical carry-look ahead adder in Figure 5.18 of the book (Slide 5 of Module 44): The gate delay for G0 is The gate delay for P0 is The gate delay for G1 is The gate delay for P1 is The gate delay for G2 is The gate delay for P2 is The gate delay for G3 is The gate delay for P4 is The gate delay for c8 is The gate delay for c32 is The gate delay for the internal carries in Block 1 is The gate delay for the sum in Block 2 is The critical path delay for this 32-bit hierarchical carry-lookahead adder is gate delays. If we used the same design for a 64-bit hierarchical carry-lookahead adder the critical path delay would by gate delays.

2 1 2 1 2 1 2 1 2 2 2 1 8 8

For a double-precision 64-bit binary floating-point number in IEEE format: The approximate exponent range is 10± The approximate precision is digits For a single-precision 32-bit binary floating-point number in IEEE format: The approximate exponent range is 10± The approximate precision is digits

308 16 38 7

Consider a 5-bit array multiplier for unsigned binary numbers based on the general design, of which a 4-bit example is depicted in Figure 5.32 (Slide 5, Module 45). The 5-bit array multiplier will have rows. Each row will consist of blocks. The gate delay to generate m1 and q1 is . The gate delay to generate the carry-out in each full-adder (FA) is . The critical path in a 5-bit array multiplier is full-adders. The total gate delay for a 5-bit array multiplier is gates. Let x and y be 5-bit unsigned numbers. Assume the gate delay is 1 ns. If x =1 and y = 5, it will take a 5-bit array multiplier ns to multiply x and y. If x = 31 and y = 26, it will take a 5-bit array multiplier ns to multiply x by y.

4 5 1 2 11 23 23 23

Assume we design an adder/subtractor like we did before, but we use a carry-lookahead adder instead of a ripple-carry adder. How many gate delays will a 16-bit adder/subtractor have? If we add an XOR gate to detect overflow, how many gate delays will an 8-bit adder/subtractor have? If the gate is 50 ns, how many operations (addition or subtraction) can a 32-bit adder/subtractor which detects overflow perform in a second? (Round to the nearest integer). How many operations can a 64-bit adder/subtractor with overflow detection perform in a second? (Round to the nearest integer).

4 5 4000000 4000000

Assume the gate delay is 50 ns. (1 ns = 10-9 seconds). Enter all numbers as integers (i.e., no commas or decimal points) The critical-path delay through a 4-bit ripple-carry adder is ns. The critical-path delay through the 4-bit adder/subtractor we designed is ns. The critical-path delay through the 4-bit adder/subtractor that detects overflow is ns. The 4-bit adder/subtractor that detects overflow can perform additions or subtractions per second.

400 450 500 2,000,000

The first 14 digits of π are: 3.1415926535898. Which IEEE floating-point formats could be used to represent this number? Single precision Either single or double precision Neither. The number has too many digits. Double precision Neither. The number is too small.

Double precision

From the list below fill in the steps for converting an AND-OR circuit to one with all NAND gates: Step 1: Step 2: Step 3: Step 4: A. Use DeMorgan's theorem to convert AND gates to NOR gates. B. Use DeMorgan's theorem to convert OR gates to NAND gates. C. Use double inversion to invert inputs of AND gates D. Use double inversion to invert inputs of OR gates E. Use double inversion to invert outputs of AND gates F. Use double inversion to invert outputs of OR gates G. Use NAND gates to realize necessary inversions. H. Use NOR gates to realize necessary inversions.

E, D, B, G

Referring to Figure 6.1(a) in the book or Module 49, Slide 12(a)). Enter your answers in alphabetic order with no spaces. For example: a+b!c Given: f = !a(b+!c) + a(b!c) s = 0 = 1 = Given: f = !b(!c) + b(a) s = 0 = 1 =

a b+!c b!c b !c a