Microcontrollers Spring 2023

human interface devices

Example is Video display terminal, printers, keyboard, mouse

Parity Bit (P) is automatically set or cleared each machine cycle to est. even parity with the ACC

# of 1-bits in the ACC and the parity bit is always even

A computers has 2 key traits

1. ability to operate on data without human interaction 2. ability to store and retrieve data

Carry flag (C or CY) is dual purpose, it is used in which ways?

1. in traditional way for arithmetic operations, set if there is a carry out of bit 7 during an add, or set if there is a borrow into but 7 during a subtract example: if ACC contains FFh, then instruction ADD A,#1 will leave ACC equal to 00h and sets carry flag in PSW 2. Carry flag is also " Boolean Accumulator", serving as a 1-bit register for Boolean instruction operating on bits: example: the following instruction ANDs bit 25H with the carry flag and places the result back in the carry flag: ANL C,25H

Internal RAM of the 8051 has two special features:

1. the registers and input/output ports are memory mapped and accessible like any other mem. location and 2. the stack resides within the internal RAM rather than ext. RAM ( opposite of microprocessor) figure of on chip data mem. ; internal storage divided b/t internal RAM (00h-7Fh) and special function registers (80h-FFh) 8051's internal data memory space has range from 00h-FFh (256bytes) - only half of the internal mem. space is for general data (00h-7Fh) while upper half (80h-FFh) is for specific purposes and not general data; therefore only loser half considered internal RAM Internal data RAM further subdivided into register banks (00h-1Fh), bit addressable RAM (20h-2Fh), and general purpose RAM (30h-7Fh)

Steps the CPU takes to fetch instructions from systems RAM or ROM

1.) contents of program counter are placed on address bus 2.) a READ control signal is activated, 3.) data (instruction opcode) are read from RAM and placed on the data bus 4.) the opcode is latched into the CPUs internal instruction register 5.) program counter is incremented to prepare for the next fetch from memory

What is the address of reg. 5 in reg. bank 3

1Dh

With the oscillator clk as ref. how many clk cycles does the 8051 need to perform a discrete op.?

2; a discrete operation could be fetching an instruction, decoding, or executing instruction duration of two clk cycles called a state

A 16-bit address bus can access...

2^16 addresses locations or 2^6 x 2^10 = 64K locations, where K stand for 2^10 = 1024 a 20bit address bus can access 2^20 locations or 1M = 1024k

Given n address lines, how many locations can the CPU access?

2^n

8051 Pin out

32 pins of 40 are I/O port lines, 24 of which are dual purpose - each can op. as I/O, or as a control line or part of the address or data bus designs requiring min. ext. mem. or other ext. components use these 32 ports for general purpose - 8 lines in each port can be treated as a unit in interfacing to parallel devices (like printers and DAC) - or each line can op. indep. in interfacing to single bit devices like switches, LEDs, ..etc.

MCS-51 Family of microcontrollers IC's made by Intel - We focus on 8051 and its features

4K bytes ROM (MROM) 128bytes RAM 4 8-bit I/O ports 2 16-bit timers Serial Interface 64K external code memory space 64K external data memory space Boolean processor (operates on single bit) 210 bit-addressable locations 4 microsecond multiply/divide

Example: what is the state of the P bit after execution of the following instruction? MOV A,#55H

55H = 01010101 therefore P = 0 because already have even number of 1-bits

in order for 8051 to fully processes an instruction it requires how many states?

6 states (12 clk cycles) since it has to fetch and decode instruction and then execute instruction duration of 6 states is called one machine cycle; more complex instructions would take more than one machine cycle to carry out oscilator cycles (p), states(s)

At byte location 20H thru 2Fh, how many general purpose bit addressable locations are there?

8 bits/byte x 16 bytes addresses= 128 bits these 128 general purpose bit addressable location are accessed as bytes or as bits, depending on instruction

bottom 32 location of internal mem. contain the reg. banks, the 8051 instructions set supports..

8 reg's R0 through R7, by default these reg's are at addresses 00h - 07H

TImer Registers

8051 contains 2 16bit timer/counters for timing intervals or counting intervals TImer 0 is at addresses 8AH (TL0,low-byte) and 8CH (TH0, high-byte) TImer 1 is at addresses 8BH (TL1, low byte) and 8DH (TH1, high byte) timer operation is set by timer mode register TMOD at address 89H timer control register TCON at 88H (only this one is bit addressable)

Serial port REgisters

8051 contains on chip serial port for communication with serial devices like terminals or modems or other ICs serial interfaces (AD converters, shift registers) SBUF (serial data buffer) at 99H holds both transmit data and receive data - writing to SBUF loads data for transmission; reading to SBUF accesses received data

What instruction would be used to initialize the stack pointer on the 8052 to create a 48 byte stack at the top if internal memory?

8052 as twice the internal ram as 8051 there RAM goes from 00h to FFh, if we want a 48 byte stack at top of internal memory we do FFh - 30h (because 48decimal = 30hex) = CFh Both end of range count as a location so, if we start stack at CFh we would have a 49 byte stack, BUT the stack increments by one before writing, so stack actually writes data to D0, hence starting stack at CFh is correct since it increments 1 before writing data upon reassuring system , stack starts at 07H, there fore bank 1 and above will b used for stack, unless you move it else where MOV SP,#0CFH 48 byte stack positioned at top occupies D0H to FFH since SP increments before the first item is placed on the stack, it should be initialized to the address just below the starting location, CFH

How much ROM do most computer systems contain?

A small amount, just enough to hold the short, frequently used software routines that perform in/output operations

what is the state of the auxiliary carry flag and the content of the accumulator after execution of the instruction sequence below? MOV R5,#1 MOV A,#9 ADD A,R5

AC = 1, ACC = 0AH 00000001 + 00001001 = 00001010 so ACC = 0AH low order nibble of the result 1010B = AH > 9H, so AC is set if addition instruction is followed by a decimal adjust instruction (DAA), the final result in the accumulator is 00010000B = 10H which is the correct result

PSEN* Program store enable is what?

An output signal on pin 29 that is the control signal that enables external program (code) memory connects to EPROM output enable EO* to permit reading of program bytes PSEN* single pulses low during fetch stage of an instruction, which is stored in external program memory binary code of a program (the opcode) are read from EPROM, travel across data bus, and are latched into the 8051's intruction reg. for decoding When executing a program from internal ROM, PSEN* remains inactive (high)

Why is the number of lines (width) of the data bus important of a computer's performance?

Because a computer spends around 2/3 of its time moving data and the majority of move operation are b/t a CPU register and external RAM or ROM Limitation by width is a bottleneck 16bit computer means the computer has 16 lines on its data bus computing power increases as the width of the data bus increases

What is the state of the carry flag and the content of the accumulator after the execution of the following instruction sequence? MOV R5,#55H MOV A,#0AAH ADD A,R5

C = 0, ACC = FFH because 0101 0101 (R5 = RRH) + 1010 1010 (ACC = AAH) = 1111 1111 = FFh no carry generated, so carry bit is cleared

RST (Reset)

RST input is on pin 9 for master reset of 8051, when signal brought High for at least two machine cycles, the 8051 internal reg's are loaded with appropriate values for an ordinary sys start-up for normal op. RST held low

Write operation does what?

CPU outputs data on the data bus, because of the control signal, memory recognizes the operation as a write cycle and stores the data in the location specified

What are I/O devices?

Computer peripherals, provide a path for communication b/t the computer system and the "real world" have three classes : mass storage, Human interface, control/monitor

EA* External Access

EA* signal on pin 31 is generally tied high or low, if high, 8051/52 executes programs form internal ROM when executing in the lower 4K/8K of memory if low, programs execute from external memory only (and PSEN* pulses low accordingly) and internal ROM is disabled and programs execute from external EPROM

What is the state of the overflow flag and the content of the ACC after the execution of : MOV R7,#0FFH MOV A,#0FH ADD A,R7

OV = 0, ACC = 0EH R7 intialized with FFH with as signed number equals -1(decimal), ACC initialized to 15, therefore 14 = 0EH in ACC

Three levels of software b/t the user and the hardware of a computer system:

Lowest level directly manipulates the hardware of the system; reading characters from the keyboard or from a disk, writing characters to the screen; usually stored in ROM ( the BIOS - basic input output system)

To read contents of internal RAM address 5Fh into the accumulator, following instruction used:

MOV A,5FH instruction moves a byte of data using direct addressing to specify the "source location" (address 5Fh), destination is implicitly specified in instruction opcode as A the accumulator

How to read the contents of address 05h into the accumulator, apply following instruction:

MOV A,R5 this is a one byte instruction upon register addressing or same thing but as a 2byte instruction using the Diest address as byte 2: MOV A,05H

Internal RAM can also be accessed using indirect addressing through R0 or R1, for example the following two instructions perform the same operation as the single instruction for direct addressing:

MOV R0,#5FH (immediate addressing to move 5Fh value into reg. R0) MOV A,@R0 (uses indirect addressing to move the data "pointed at by R0" into the accumulator

Active register bank may be altered by changing the register bank select bits in the program status word. Assuming then, that the register bank 2 is active, the following instruction writes the contents of the accumulator in to location 18h:

MOV R0,A idea of register banks permits fast and effective context switching, where by separate sections of software use a private set of registers indep. of other sections of software

Family of Microcontrollers used in class

MSC-51

Here do control programs reside in micro processors and microcontrollers?

Microprocessors implement a shared memory space for data and programs ; for microcontrollers are employed as the central component in control oriented designs; due to limited mem, there is no disk drive or OS so the control program will be found in the ROM

8051 has four dedicated control bus signal, what are they?

PSEN* (Program store enable) ALE (address latch enable) EA* (External Access) RST (Reset)

Simplified View of CPU

Registers store temporary info. Arithmetic logic unit (ALU) performs operations on info in registers instruction decode and control unit determines operation to perform and sets up operation Instruction register (IR) holds binary code for each instruction as it is executed program counter (PC) holds the memory address of the next instruction to be executed

How many specific registers are there in the 8051?

R0 to R7 and another 21 special function registers (SFRs) at the top of internal RAM from addresses 80h to FFh. (most of the 128 address are not defined, only 21 are on the 8051)

The memory devices directly accessible by the CPU consists of semiconductor IC's called

RAM and ROM RAM is volatile, ROM is nonvolatile

User programs and data are stored on disk and are loaded into ... for execution

RAM, computer systems typically contain millions of bytes of RAM

THe 8051 internal registers are configured as part of the on chop

RAM, therefore each register also has an address (except the program counter and instruction register as they are rarely manipulated)

Overflow flag (OV) is set after an addition or bus traction op. if there was an arithmetic overflow; used with signed numbers, when unsigned number used just ignore this bit;

Results greater than +127 and less than -128 set the overflow bit

Read operation does what?

Retrieves a byte of data from memory at the location specified and places it on data bus CPU reads the data and places it in one of the internal registers

What instruction could be used to set the MSB in the B accumulator while leaving the other bits intact?

SETB 0F7H since F7h is the bit address in byte address F0h we want to set

What instruction would you use to set bit 3 in byte address 25h?

SETB 2Bh (note LSB is but 0 so bit 3 is the fourth bit in the row from the left)

to set bit 67h uses this instructions

SETB 67H not that bit address 67h is MSB at byte address 2Ch the instruction above has no effect on the other bits at this address

Dot operator

SETB P1.7 it addresses a bit within a bit addressable byte location

Illustrate an instruction sequence to make register bank 2 the active register bank, assume that the previously active register bank is unknown:

SETB RS1 CLR RS0 result of this is to place 10(binary) = 2(decimal) in reg. bank select bits in the program status word

Stack Pointer (SP) is an 8-bit register at address 81H, it contain the address of the data item currently on top of the stack

Stack operations include pushing data onto the stack (increments the SP before writing data) and popping data off the stack (reads data and then decrements the SP) 8051 stack is kept in internal RAM and is limited to addresses accessible by indirect addressing, first 128 bytes of the on chip RAM (full 256 on the 8052), you control where it is by placing the address in SP, stack is FILO, first in, last out to initialize the SP with stack beginning at 60H, the following instruction used: MOV SP,#5FH (since it increments before writing data so it starts are 5Fh and data starts ar 60h) this limits stack to 32 bytes, since uppermost address of on chip RAM is 7FH, the value of 5FH is used since the SP increments to 60H before the first push operation stack is access explicitly by the PUSH and POP instructions to temporarily store and retrieve data, or implicitly by the subroutine call (ACALL LCALL) and return (RET,RETI) instruction to save and restore the program counter usually store flags in the stack like: PUSH A PUSH PSW to get off stack POP PSW POP A

8051's on chip oscillator is driven typically by a 12MHz crystal so one clk pulse is

T = 1/f = 83.33ns one machine cycle consists of 12 such clk pulses, hence its duration is 83.33ns X 12 = 1microsecond

What are control signals?

Timing signals supplied by the CPU to synchronize the movement of info on the address and data buses Usual signals are CLOCK, READ, WRITE

What does WAIT: JB P1.5,WAIT Mean?

if the bit P1.5 is set, jump to the label WAIT, in other words jump back and check it again waits for device to be ready

What is a bus?

a collection of wires carrying info. with a common purpose

Flag 0 (F0) is what type of flag?>

a general purpose flag bit available for user applications

What is an operating system?

a large collection of programs that come with the computer system and provide the mechanism to access, manage, and effectively utilize the computer's resources - these abilities exist through the OS's command language and utility programs

What is a program?

a series of instruction to perform a meaningful task also called software

What are the power connections for the 8051?

a single 5V supply, Vcc connected to pin 40 and Vss (GND) connected to pin 20

Register Bank Select bits (RS0 and RS1) determine the

active register bank. Example: following three instructions enable register bank 3 and then move the content to R7 (byte address 1FH) to ACC SETB RS1 SETB RS0 MOV A,R7 set's make. a 11(binary = 3(decimal) that's how it enables register bank 3 when program assembled, correct bit addresses are substituted for symbols RS! RS0 and the instruction SETB RS1 is same as SETB 0D4H

Access to the circuity around the CPU is provided by three buses:

address, data, and control For each READ/WRITE op. , CPU specifies location of the data by placing an address on the address bus and then activates a signal on the control bus, indicating whether the operation is a read or write

General Purpose RAM

although there is only 80 bytes of general purpose RAM, addresses 30h-7Fh, the lose 48 bytes can be used similarly - though they do have other purposes

Instructions for a CPU are usually..

arithmetic, logic, data movement, and branch operations - all represented by binary codes called instruction set

CPU has the ability to understand and execute instructions based on a set of

binary codes, each representing a simple op.

How are internal registers accessed on microprocessors?

by an instruction set like INCA - this instruction increments the contents of the A accumulator operation is implied implicitly within the instruction opcode similar access to registers is also used on the 8051 microcontrollers, INC A performs same operation

Bit addressable RAM; 8051 contain 210 such locations, 128 are byte addresses 20h-2Fh and the rest are in special function reg's

can individually access bits through software; bits can be cleared , ANDed, ORed,.. with single instruction microprocessors need read-modify-write sequence of instructions to do this 8051 I/O ports are bit addressable therefore simplifying the software interface to single bit in/outputs

What does the data bus do?

carries info. b/t CPU and memory or b/t CPU and I/O devices

CPU's execution stage involves

decoding the opcode and generating control signals to gate internal registers in and out of the ALU and to signal the ALU to perform specified operation simplified steps

Most special function registers (SFRs) are accessed by .... addressing.

direct Some are both bit-addressable and byte-addressable

Which address modes can freely access any location in general purpose RAM?

direct or indirect addressing modes

On-chip oscillater for 8051

driven by crystal connected to pins 18-19, also has stabilizing capacitors nominal crystal freq. is 12MHz for most ICs in the MCS-51 family

Port 3 on the 8051

dual purpose port on pins 10-17, is general purpose I/O, pins are multi-functional - each having an alternate purpose related to special features of the 8051

Chapter2

hardware Summary

Microprocessors Vs Microcontrollers

hardware architecture: microprocessor is a single chip CPU, while a microcontroller contains a single IC, a CPU and other circuitry (parts in IC of microcontroller are in the dotted line) microcontroller have built in interrupt system because they are used for fast contact switching, suspending one process while executing another in response to an event (like opening a microwave door) Applications: microprocessors used as CPU in microcomputer systems; suited for processing info in computer systems microcontrollers are found in small, minimum component designs performing control oriented activities, reduces overall component count; suited to control I/O devices Instruction Set features: microprocessor instruction are "processing intensive" (instructions cater towards operating large volumes of data), instruction operate on nibbles, bytes, words, double words (32bits) microcontrollers have instruction sets catering to control of in/outputs, interface to many in/outputs uses a single bit (motor may be turned on/off by 1-bit output port to solenoid) microcontrollers have built in circuity and instructions for I/O operations, event timing, enabling,interruputs caused by external stimuli microprocessors require additional circuity to perform operations that a microcontroller can processing power of microcontroller is much less then microprocessor instruction in on chip ROM for microcontroller, microcontrollers are permanently programmed for one task Computer systems have a high RAM to ROM ratio microcontroller have a high ROM to RAM ratio; control program stored in ROM permanently - called firmware

Mass storage devices

hold large quantities of info (programs or data) that can't fit into computers small RAM (main memory), therefore info must be loaded into main memory before CPU accesses it Two types: 1.) online storage - on magnetic disk, is available to CPU w/o human intervention upon request of a program 2.) archival storage

Port 1 on the 8051

is a dedicated I/O port on pins 1-8, the pins are available for interfacing to ext. devices as required these pins used solely for interfacing to ext. devices (exceptions for 8032/52)

Port 0 on the 8051

is dual purpose on pins 32-39 in min. designs its used as a general purpose I/O port for larger designs with ext. mem. it becomes a multiplexed address and data bus

What is a CPU?

it is just a collection of logic circuits that continuously performs two operations: 1. fetch instructions 2. execute instructions

Classification of computers:

micro, mini, mainframe microcomputers: CPU is contained within a single IC, a microprocessor; execute one program with only one user at a time; Mini/mainframe computers have CPU's contained within multiple IC's; several IC's mini, several circuit boards mainframe; both are multitasking systems

B register, accumulator B at address F0H is used along with the ACC for

multiply and divide operations MULAB instruction multiples 8-bit unsigned values in A and B and leaves the 16-bit result in A (low byte) and B(high byte) the DIV AB instruction divides A by B, leaving the integer result in A and the remained in B B register can also be treated as a general purpose scratch pad register it is bit addressable through bit addresses F0H to F7H BxA = BA, B/A = A rB

What does the internal mem. of a 8051 consists of?

on chip ROM and on chip data RAM (RAM here contains general purpose storage, bit addressable storage, reg. banks, and special function reg.'s)

ALE adress latch enable

on pin 30, 8051 uses ALE for demultiplexing the address and data bus, when port 0 is in its alternate mode ( as the data bus and the low-byte of the address bus) ALE is the signal that latches the address into an external reg. during the first half of the memory cycle - once done the the Port 0 lines are then available for data input or output during the second half of the mem cycle, when the data transfer takes place ALE signal pulses at 1/6th the on-chip oscillator freq. and can be used as a general purpose clk for the rest of the system, if 8051 is clked from a 12MHz crystal, the ALE signal oscillated at 2 MHz (exception during the MOVX signal when one LAE pulse is missed) also used for programming input pulse from EPROM version of the 8051

What does a computer system consist of?

peripheral devices for communicating with humans, programs to process data equipment is the hardware, programs are the software

Port 2 on the 8051

port 2 (pins 21-28) is a dual purpose port serving as general purpose I/O, or as high-byte of the address for designs with ext. code mem. or mare than 256 bytes of ext. data mem.

8051 I/O ports consists of Port 0 at address 80H, Port 1 at 90H, Port 2 at A0H, Port 3 at B0H

ports 0,2,3 may not be available for I/O if exit. mem is used or if some 8051 special features are used (interrupts..) P1.2 and P1.7 are always available for general purpose I/o lines all port bits are bit-addressable ; for example this means you could turn on a motor by SETB P1.7 or turn it off by CLR P1.7 the above instructions use the dot operator to address bait within a bit - addressable byte location, assembler performs conversion , therefore the following two instruction ar the same CLR P1.7 and CLR 97H there are FF on connected to the port pins (how they hold their logic level), so there are 32 total FF's b/c 32 port pins

the 8051 implements separate mem for

programs (code) and data

microcontroller operation for a NAND gate example with code

propagation delay is longer than a NAND gate by itself (1-17ms to about 10ns)

What does SETB 0E0H do?

sets bit 0 in the accumulator, leaves other bits unchanged note that E0h is both the byte address of the entire accumulator and the bit address of the LSB in the accumulator since SETB instruction operates on BITS (NOT BYTES) only the address is affected Port 1 is at byte address 90h or 10010000B, the bits within Port 1 have addresses 90h to 97h or 10010xxxB

microprocessors are

single chip CPUs used in microcomputers

Program Status Word (PSW) contains

status bits

What forms the basis of the 8051's timing and synchronization?

the 12MHz cystal (12 million clk cycles /sec), every op. performed by 8051 is in step with these cycles

ROM in a computer contains

the BIOS (basic in/output system) software and a start up program that executes with computer turned on, and a boot strap loader routine start up program checks for options, initializes memory, performs diagostic checks, boot strap loader routine reads first track (a small program) from the disk into RAM and passes control to it, then it loads RAM-resident portion of the operating system form the disk and passes control to it (system has to pull it self up)

What par to the computer system is the brains that administers all activity in the system and performs all operations on data?

the CPU

Data pointer (DPTR)

used to access external code or data memory, is a 16-but reg. at address 82H (DPL, low byte) and 83H (DPH, high byte) (allows up to an external RAM of 64K = 65536 = 2^16) following instruction writes 55H into external RAM location 1000H; MOV A,#55H MOV DPTR,#1000H MOXV @DPTR,A 1st instruction uses immediate addressing to load data constant 55H into the accumulator 2nd line also uses immediate addressing to load 16-bit address constant 1000H into data pointer 3rd line uses indirect addressing to move the value in A (55H) to external RAM location whose address is in DPTR (1000H). X in the mnemonic MOVX indicates that th move instruction accesses external data memory

Control/Monitor Devices

using these computers can perform control oriented tasks like temperature control, elevator control,.. control devices are outputs (actuators) that can affect the world around them when powered (like motors ) monitoring devices (sensors) are stimulated by heat, light, pressure,.., and convert this energy to a voltage or current read by the computer (thermistors, switches,,..); interface circuitry converts the voltage or current to binary data

Auxiliary carry flag

when adding binary coded decimal (BCD) values, the auxiliary carry flag (AC) is set if a carry was generated out of bit 3 into but 4 or if the result in the lower nibble is in the range 0AH-0FH if values added are BCD, then the add instruction must be followed by DAA (decimal adjust accumulator) to bring results greater than 9 back into range

I/O port structure of the 8051

writing to a port pin loads data into a port latch that drives a field effect transistor connected to the port pin drive capacity is 4low power Schottky TTL loads for Ports 1,2,3; 8 LS loads for Port 0; ext. pull up resistor may be needed depending on the input char. of the devices driven by the port pin there is a read latch and read pin capability instr. that req. a reading modify write op (CPL P1.5) read the latch to avoid misinterpreting the volt. level in the event the pin is heavily loaded inst. that input a port but (MOV C,Pl.5) read the pin and the port latch must contain a 1 in this case, otherwise the FET driver is on and pulls tile output low sys. reset sets all port latches, so port pins may be used as input w/o explicitly setting tile port latches (if port latch is cleared (CLR P1.5) then it cannot function subsequently as an input unless latch is set first (SETB Pl.5)