Microprocessor System (MCSL51E) - Chapter 2: The Microprocessor and its Architecture

AX

A 16-bit accumulator/register.

EAX

A 32-bit accumulator/register.

RAX

A 64-bit accumulator/register.

Count (RCX)

A general-purpose register that also holds the count for various instructions.

Data (RDX)

A general-purpose register that holds a part of the result from a multiplication or part of dividend before a division.

Base Address, Limit, Access Rights Byte

A protected mode descriptor contains these three.

Segment Address, Offset Address

All real mode memory addresses must consist of these two addresses.

Page Tables

DOS and EMM386.EXE use these to redefine memory between locations C8000H-EFFFFH as upper memory blocks.

Program-Invisible Portion

Each segment register contains this to be used in the protected mode. It is often called cache memory because cache is any memory that stores information.

TLB (translation look-aside buffer)

Intel has incorporated this special type of cache because re-paging a 4K-byte section of memory requires access to the page directory and a page table, both located in memory. This caches the 32 most recent page table translations.

Granularity Bit (G)

It allows a segment length of 4K to 4G bytes in steps of 4K bytes.

Memory Paging Mechanism

It allows any physical memory location to be assigned to any linear address.

Cache

It allows the microprocessor to access the memory segment without again referring to the descriptor table until the segment register's contents are changed.

Thread

It consists of a program counter, a register set, and a stack space.

Access Rights Byte

It defines how the memory segment is accessed via a program.

Segment Address

It defines the beginning address of any 64K-byte memory segment.

Limit

It defines the last location of the segment.

Descriptor

It describes the memory segment's location, length, and access rights. It is located in the segment register & describes the location, length, and access rights of the segment of memory.

Task Register (TR)

It holds a selector, which accesses a descriptor that defines a task.

VIF (virtual interrupt)

It is a copy of the interrupt flag bit available to the Pentium 4.

Relocatable Data

It is a data that can be placed in any area of memory and used without any change to the program.

Global Descriptor / System Descriptor

It is a descriptor that contain segment definitions that apply to all programs.

Local Descriptors / Application Descriptor

It is a descriptor that is usually unique to an application.

AC (alignment check)

It is a flag bit that activates if a word or doubleword is addressed on a non-word or non-doubleword boundary.

I (interrupt) flag

It is a flag bit that controls operation of the INTR (interrupt request) input pin.

T (trap) flag

It is a flag bit that enables trapping through an on-chip debugging feature.

S (sign) flag

It is a flag bit that holds the arithmetic sign of the result after an arithmetic or logic instruction executes.

A (auxiliary carry) flag

It is a flag bit that holds the carry (half-carry) after addition or the borrow after subtraction between bit positions 3 and 4 of the result.

C (carry) flag

It is a flag bit that holds the carry after addition or the borrow after subtraction.

ID (identification)

It is a flag bit that indicates that the Pentium microprocessors support the CPUID instruction.

NT (nested task) flag

It is a flag bit that indicates the current task is nested within another task in protected mode operation.

P (parity) flag

It is a flag bit that is the count of ones in a number expressed as even or odd. Logic 0 for odd parity; logic 1 for even parity.

IOPL (privilege level for I/O devices) flag

It is a flag bit that is used in protected mode operation to select the privilege level for I/O devices.

RF (resume)

It is a flag bit that is used with debugging to control resumption of execution after the next instruction.

O (overflow) flag

It is a flag bit that occurs when signed numbers are added or subtracted. It indicates that the result has exceeded the capacity of the machine.

VIP (virtual interrupt pending)

It is a flag bit that provides information about a virtual mode interrupt for Pentium; used in multitasking environments.

D (direction) flag

It is a flag bit that selects increment or decrement mode for the DI and/or SI registers.

VM (virtual mode)

It is a flag bit that selects virtual mode operation in a protected mode system.

Z (zero) flag

It is a flag bit that shows that the result of an arithmetic or logic operation is zero.

Program Invisible

It is a programming model wherein registers are not addressable directly during applications programming.

Program Visible

It is a programming model wherein registers are used during programming and are specified by the instructions. Examples are Intel 8086 and Intel Core 2.

Destination Index (RDI)

It is a register that often addresses string destination data for the string instructions

Base Pointer (RBP)

It is a register that points to a memory location for memory data transfers.

Descriptor Zero

It is called the null descriptor, must contain all zeros, and may not be used for accessing memory.

Linear Address

It is defined as the address generated by a program.

Stack Entry Point

It is determined by the stack segment and stack pointer registers.

Privilege Level Violation

It is indicated by the system if privilege levels are violated.

Stack Data

It is referenced through the stack segment at the memory location addressed by either the stack pointer (SP/ESP) or the pointer (BP/EBP).

Physical Address

It is the actual memory location accessed by a program.

Source Index (RSI)

It is the register that addresses source string data for the string instructions; also functions as a general-purpose register.

Accumulator (RAX)

It is the register used for instructions such as multiplication, division, and some of the adjustment instructions.

Stack Pointer (RSP)

It is the special-purpose register that addresses an area of memory called the stack. It stores data through this pointer.

Instruction Pointer (RIP)

It is the special-purpose register that addresses the next instruction in a section of memory, and defined as a code segment.

Flags (RFLAGS)

It is the special-purpose register that indicates the condition of the microprocessor and controls its operation. It is upward-compatible from the 8086/8088 through Core2. It never changes for any data transfer or program control operation.

Selector

It selects a descriptor from a descriptor table in place of a segment address.

Offset Address

It selects any location within the 64K byte memory segment. Also called displacement. It is always added to the segment starting address to locate the data.

Task

It shares with peer threads its code section, data section, and operating system resources.

AX, BX, CX, DX, SP, BP, DI, SI

List of 16-bit registers (8).

EAX, EBX, ECX, EDX, ESP, EBP, EDI, ESI

List of 32-bit registers (8).

RAX, RBX, RCX, RDX, RBP, RDI, RSI

List of 64-bit multipurpose registers (7).

RAX, RBX, RCX, RDX, RSP, RBP, RDI, RSI, R8 to R15

List of 64-bit registers (23).

AH, AL, BH, BL, CH, CL, DH, DL

List of 8-bit registers (8).

C, P, A, Z, S, T, I, D, O, IOP1. IOP0, NT, RF, VM, AC, VIF, VIP, ID

List of Flag Bits (18).

CS, DS, ES, SS, FS, GS

List of Segment Registers (6).

Instruction Pointer (RIP), Stack Pointer (RSP), Flags (RFLAGS)

List of Special-Purpose Registers (3).

CR0, CR3

Memory paging is accomplished through these control registers.

Win32

Most Windows applications use this 32-bit environment.

Ending Address

Once the beginning address is known, this address is found by adding FFFFH.

Directory, Page Table, Offset

The linear address, as generated by software, is broken into three sections that are used to access the page directory entry, page table entry, and memory page offset address.

Base Index (RBX)

The register that sometimes holds offset address of a location in the memory system in all versions of the microprocessor.

FS, GS

These are supplemental segment registers available in 80386-Core2 microprocessors. It allow two additional memory segments for access by programs. Windows uses these segments for internal operations, but no definition of their usage is available.

GDTR (global descriptor table register), IDTR (interrupt descriptor table register)

These contain the base address of the descriptor table and its limit.

Segment Registers

These registers generate memory addresses when combined with other registers in the microprocessor. It functions differently in real mode than in protected mode.

Selector

This accesses global descriptor table, & loads local descriptor table address, limit, & access rights into the cache portion of the LDTR.

Base Address

This address of the descriptor indicates the starting location of the memory segment.

Segment plus offset addressing scheme

This addressing scheme allows DOS programs to be relocated in memory.

Program Loader

This automatically handles program loading. It is within DOS.

Access Rights Byte

This controls access to the protected mode segment. It describes segment function in the system and allows complete control over the segment. If the segment is a data segment, the direction of growth is specified

1M byte

This first amount of memory is called the real memory, conventional memory, or DOS memory system

Transient Program Area (TPA)

This holds the DOS (disk operating system) operating system; other programs that control the computer system.

Protection Fault

This indicates if the segment grows beyond its limit, the operating system is interrupted.

Free-Pointer

This indicates the area of memory, and is maintained by DOS.

CPUID

This instruction provides the system with information about the Pentium microprocessor

Memory Paging

This invisibly translates a linear address to any physical address.

SS (stack)

This is a segment register defines the area of memory used for the stack.

ES (extra)

This is a segment register that is an additional data segment used by some instructions to hold destination data.

LDTR (local descriptor table register)

This is loaded with a selector to access the local descriptor table.

Paragraph Boundary Limitation

This limitation is removed in protected mode.

Instruction Pointer

This locates the next instruction within the code segment.

Extended Memory System (XMS)

This memory system is accessed via a segment address plus an offset address, just as in the real mode.

Flat Mode Memory System

This memory system is one in which there is no segmentation. It does not use a segment register to address a location in the memory. It contains 1T byte of memory using a 40-bit address.

Protected Mode Memory Addressing

This mode of addressing allows access to data and programs located within & above the first 1M byte of memory. It is where Windows operates.

Real Mode Operation

This mode of operation allows addressing of only the first 1M byte of memory space—even in Pentium 4 or Core2 microprocessor.

Relocatable Program

This program is one that can be placed into any area of memory and executed without change.

Code Segment Register

This register defines the start of the code segment.

Requested Privilege Level (RPL)

This requests the access privilege level of a memory segment.

DS (data)

This segment register contains most data used by a program. Data are accessed by an offset address or contents of other registers that hold the offset address.

CS (code)

This segment register holds code (programs and procedures) used by the microprocessor.

TI bit

This selects either the global or the local descriptor table.

AH, AL

Two 8-bit accumulator/registers.