Quiz 2 questions

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Cache memory is based on the concept of using a large, fast, and expensive memory to supplement the workings of main memory.

False

Dual core or quad core multi-core chips are larger than a single-processor chip but produce less current leakage and heat.

False

Paged memory allocation offers the advantage that it doesn't require the entire job to be stored in memory during its execution.

False

The key to the successful implementation of demand paging is the use of a high-speed CPU

False

The key to the successful implementation of demand paging is the use of a high-speed CPU.

False

The shortest remaining time (SRT) algorithm is often used in interactive systems.

False

Thrashing is a problem that occurs when there are a large number of jobs and many free pages so that pages are being moved around too much.

False

When using a FIFO scheme, adding more memory always results in better performance.

False

When using priority scheduling, priorities are assigned to jobs by the owner of the job (the user).

False

The ____ is also called a high-level scheduler.

Job Scheduler

Each thread in a process is represented by a data structure called a ____ that contains basic information such as the thread's unique identification, state, and priority.

Thread Control Block

A variation of the LRU page replacement algorithm known as the clock page replacement policy is implemented using a pointer to step through the reference bits of the active pages, simulating a clockwise motion.

True

Associative memory is a name given to several hardware registers that are allocated to each active job whose task is to associate segment and page numbers belonging to the job being processed with their main memory addresses.

True

Context switching is required by all preemptive algorithms

True

In Round Robin scheduling, if processing isn't finished when time expires, the job is preempted and put at the end of the READY queue and its information is saved in its Process Control Block.

True

In the bit-shifting variation of the LRU page replacement policy, the process of shifting bits to the right and resetting the leftmost bit to 1 when a page is referenced gives a history of each page's usage.

True

Shortest job next (SJN) is a nonpreemptive scheduling algorithm (also known as shortest job first, or SJF) that handles jobs based on the length of their CPU cycle time.

True

The Job Table (JT) contains two values for each active job: the size of the job and the memory location where its Page Map Table is stored.

True

The optimal selection of cache size and replacement algorithm can result in 80 to 90 percent of all requests being in the cache.

True

Virtual memory can be implemented with both paging and segmentation.

True

When using a multiple-level queue strategy, aging is used to ensure that jobs in lower-level queues will eventually complete their execution.

True

____ allows for faster turnaround of CPU-bound jobs.

Variable time quantum per queue

____ effectively removes restrictions on maximum program size.

Virtual memory

The Job Scheduler seeks to ____ when scheduling jobs.

balance CPU and I/O intensive jobs

The term "____" means that during any phase of its execution, a program references only a small fraction of its pages.

locality of reference

To access a location in memory when using segmented memory management, the address is composed of two entries: ____.

the segment number and the displacement

When the operating system detects a nonrecoverable error, the following step is performed first by the interrupt handler: ____.

the type of interrupt is described and stored

One of the most important innovations of demand paging is that it makes ____ feasible.

virtual memory

Assume that four jobs, A-D, require the CPU cycles listed below. Using the SJN algorithm, the average turnaround time is ____.Job: A B C DCPU cycle: 5 2 6 4

9.0

Assume that four jobs, A-D, are in the READY queue at Time 0 and require the CPU cycles listed below. Using the SJN algorithm, the ____ job is run first.Job: A B C DCPU cycle: 5 2 6 4

B

____ can be thought of as being an intermediary between main memory and the special-purpose registers, which are the domain of the CPU.

Cache memory

____ is a dynamic-priority preemptive scheduling algorithm built to address the critical processing requirements of real-time systems and their pressing deadlines.

Earliest Deadline First

A job's state moves from HOLD to WAITING when it's ready to run but is waiting for the CPU.

False

A program is an active entity that requires a set of resources, including a processor and special registers, to perform its function.

False

CPU-bound jobs (such as printing a series of documents) have many brief CPU cycles and long I/O cycles.

False


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