All CPE 233 Questions

1. How many different instruction formats does the program in this experiment use? Make a list of the instruction and their formats for this question.

The different instruction formats this experiment uses are: IN reg-immediate MOV reg-reg SUB reg-reg OUT reg-immediate BRN immediate

4. If you configured the timer-counter to generate an interrupt on the RAT MCU every 10ms, what is the highest frequency blink rate of an LED using that interrupt? Briefly explain your answer.

The highest frequency blink rate of an LED would be 50 Hz, because the period of the interrupt would be 20 ms, and frequency is 1/period = 1/20ms, which would be 50 Hz.

9. Is it possible to have two of the same labels in an assembly language program? Briefly but completely explain.

There cannot be more than one label of the same name because when called, the program won't know which one to loop back to.

10. Briefly but completely describe a situation where the previous subroutines be potentially useful.

These subroutines would be useful in the sense that they would allow you to save context and allow you to nest interrupts.

4. List the five RAT MCU distinct instruction formats. Explicitly state the factors that differentiate these instruction types.

-Reg/Reg : Performs operation on two register values -Reg/Imm : Performs operation on one register value & one immediate value -Imm : Branches-Reg : Modify data in one register -None : Performs operation universally, nonspecific to any register or value The number and type of operands determines the instruction type.

9. Write two subroutines: Store_CZ, and Restore_CZ. The store subroutine stores the values of C & Z to r20. The restore subroutine restores the values in r20 to the C & Z flags. Don't use more than 12 instructions total for both subroutines.

.CSEG .ORG 0x01 init: MOV r20, 0x00 ;clear CZreg MOV r0, 0x00 ;temp reg store_CZ: BREQ zset zclear: LSL r20 ;shift C val into LSB CLC ;clear carry to rep z=0 LSL r20 ;shift Z val into LSB RET zset: LSL r20 ;shift C val into LSB SEC ;set carry to rep z=1 LSL r20 ;shift Z val into LSB RET restore_CZ: LSR r20 LSR r0 LSR r20 ;restor C flag CMP r0, 0x01 ;restore Z flag RET

10. Write a RAT assembly language subroutine that swaps the values in two different registers without accessing memory or changing the value in any register other than the two registers in question. Do not use more than five instructions in your solution.

.CSEG .ORG 0x01 sub_swap: init: EXOR r1, r2 EXOR r2, r1 EXOR r1, r2

9. The particular form of the LSL and LSR instructions necessitate the need for the CLC and SEC instructions. Briefly but completely describe why this is so.

Logical shift left and logical shift right functions depend on the carry flag, as they shift the carry flag's value into the register. Therefore, you need to be able to set and clear the carry flag in order for the shift to result in the correct value.

8. Write a RAT assembly language subroutine that initializes all scratch RAM memory locations to 0xFF. Don't use ST instructions in your solution.

MY_SUB: INIT: MOV r0, 0xFF MOV r1, 0x00 ;loop count LOOP: PUSH r0 ADD r1, 0x01 ; increment address CMP r1, 0x3FF BRCC LOOP ; repeat loop if r1 <= 0x3FF RET ; done

11. The programs you worked with in this experiment were implemented as "endless loops". Using the RAT MCU assembly code, could you write a program in such a way as to stop the program from executing instructions under program control? Briefly but completely explain.

Using RAT MCU assembly code, you cannot write a program to stop the program from executing instructions under program control. The closest way to achieve this effect is to create an infinite loop that only contains a branch to itself.

7. Describe a situation where a NOP instruction or a NOP-type instruction would be useful.

NOP instructions are useful whenever you want to create a delay in the clock cycle or generate a wait.

7. Currently, the RAT MCU hardware uses Y output of the register file as a possible address to the scratch RAM. Which instructions (and forms of those instructions) actually use this connection?

ST and LD, which are reg-reg types, use the Y output of the register file as a possible address to the scratch RAM.

3. If you were not able to use a LUT for this experiment, briefly but completely describe the program you would need to write in order to translate a given BCD number into its 7-segment display equivalent.

We would make a list of the constants: ;------------------------------------------------------------- ; Segment Constants for Decimal Digits ;------------------------------------------------------------- .EQU ZERO = 0x03 .EQU ONE = 0x9F .EQU TWO = 0x25 .EQU THREE = 0x0D .EQU FOUR = 0x99 .EQU FIVE = 0x49 .EQU SIX = 0x41 .EQU SEVEN = 0x1F .EQU EIGHT = 0x01 .EQU NINE = 0x09 Then we would have a display subroutine in which it would be if-else statements depending on the BCD value, you would output the segment constant for that value.

4. In the context of using an FPGA to implement your RAT MCU, briefly but completely describe whether you can be sure of the value of the stack pointer if you don't specifically initialize it using a WSP instruction.

Without using a WSP instruction to specifically initialize the value of the stack pointer, you cannot be sure of it's value. Therefore, it is always better to initialize the stack pointer so that you know it's value throughout.

2. The prog_rom.vhd file models a ROM. Briefly examine the prog_rom.vhd code and state what particular signal assignment officially turns the model into a ROM.

Write enable being set to 0 makes the model a ROM, because it can no longer be written to as in a RAM.

6. Briefly describe a scenario in which you would you utilize the ADDC vs. the ADD assembly language instruction.

You would utilize the ADDC assembly language instruction when you want to add numbers that are larger than 8 bits, so that you can account for the overflow.

6. Write a RAT assembly language subroutine that swaps the data in two locations in scratch RAM. Registers r30 and r31 contain the addresses in scratch RAM of the two locations that require swapping. Make sure the subroutine does not permanently change any register values. Don't use an EXOR instruction in your solution.

.CSEG .ORG 0x01 sub_swap: init: PUSH r0 PUSH r1 swap: LD r1, (r30) ;load opp val into opp loc LD r0, (r31) ST r0, (r30) ;store back swapped data ST r1, (r31) POP r1 POP r0 RET

2. If the PC were to increment every clock cycle, could the prog_rom output ever show the data associated with the current value on the PC's output? In other words, could the output of the prog_rom ever be associated with the current output of the PC. Briefly but fully explain your answer.

No, the prog_rom's output is never associated with the current output of the PC because the prog_rom output is one clock cycle behind the PC. During one clock cycle, the PC loads its output into the prog_rom, and on the following clock edge, the prog_rom is able to output the value that the PC inputted at the previous clock edge because the program memory is a synchronous device. We can think of the output IR signal as a register, so the output can only change on the active clock edge.

1. Rewrite the RTL equations of Table 7 to reflect the notion of a PUSH incrementing the stack pointer and a POP decrementing the stack pointer. Additionally, add intelligent comments on whether you feel there is an advantage to doing it one way or the other.

PUSH (SP+1) ← Rd, SP ← SP + 1 POP Rd ← (SP), SP ← SP - 1 The original RTL equation for PUSH has an advantage over the RTL equations written above. If the instruction worked in the above manner, you would not be able to ever access the top of the stack. For the PUSH instruction, by incrementing the stack pointer instead of decrementing, you will not be able to push data on top of the stack because of it's new location.

6. List two instructions from the RAT instruction set that would use the PC's "FROM_STACK" input. You will need to consult the RAT MCU Assembler Manual for this question. In particular, examine the RTL associated with each instruction.

RETIE and RETID would use the PC's "FROM_STACK" input.

8. Since the AND instruction does not use the C flag, you can use it for something of your choosing. For this problem, show the VHDL code for the AND instruction if the C flag is used to describe the parity of the result; assume C = '1' indicates odd parity. Don't use any type of VHDL loop construct in this solution. Make sure your solution can calculate parity in one clock cycle.

SUM <= A and B; C <= SUM(7) xor SUM(6) xor SUM(5) xor SUM(4) xor SUM(3) xor SUM(2) xor SUM(1) xor SUM(0);

3. We refer to the scratch RAM as a "higher level" of memory compared to the register file. Briefly describes what this means in the context of the RAT MCU.

Saying that the SCR has higher level memory refers to the SCR having more memory, but operating slower than the register file, which has less memory but operates faster. The reason it operates slower is because it takes more instructions to store the desired value, since it has to wait for the instructions to get from the CU => ALU => REG =>SCR.

5. As you know, part of the interrupt architecture includes the RAT MCU automatically masking the interrupts. This being the case, why then is there a need to keep the overall output pulse length of the interrupt relatively short?

Since the ISR is so quick (on the order of nanoseconds) and the interrupt is unmasked when we return from the ISR, if the interrupt pulse is longer than the time it takes to complete the ISR, the ISR will be triggered again immediately after it returns the the main assembly process using RETIE.

1. Briefly describe at least two limitations of the RAT ALU.

THe RAT ALU is only 8 bits. In addition, it does not have a multiply or divide operation.

2. Briefly but explicitly describe how the CMP instruction allows the assembly language programmer to determine "less than", "greater than", and "equal to" relationships between the instruction's operands.

The CMP instruction subtracts the value in source register from the value in the destination register. It determines "less than" if the C flag is set, it determines "greater than" if no flags are set, and it determines "equal to" if the Z flag is set after the operation is performed.

2. Briefly but completely describe the relationship between the IN and OUT instructions and the port_IDs assigned in the RAT Wrapper VHDL model.

The IN and OUT instructions both involve reading or writing the register file, thus needing an immediate value to use as a port_ID. The port_ID is used as a select for the input mux (to choose which signals to input) as well as the decoder for updating the right registers that hold the status of the outputs.

7. Write a RAT assembly language subroutine that initializes all scratch RAM memory locations to 0x00. Don't use PUSH instructions in your solution.

.CSEG .ORG 0x01 sub_zeros: init: MOV r0, 0x00 ;set reg to 0 MOV r1, 0x00 ;initialize index count MOV r2, 0xFF ;set total loop count loop: CMP r2, r1 ;check to see if done looping BREQ done ST r0, (r1) ;store 0 in location in mem ADD r1, 0x01 ;increment index BRN loop done: ST r0, (r1) ; store 0 in very last mem loc RET

8. What would be the total bit and byte capacity of the prog_rom if you doubled the number of instructions the prog_rom could store?

36864 bit capacity 4608 byte capacity

8. Write some RAT assembly code that would effectively implement a firmware debounce for a given button. For this problem, assume the button you're debouncing is associated with the LSB of buttons addressed by port_ID 0x55. Make sure to fully describe your code with instruction comments and header comments. Also include a flowchart that models your code.

;--------------------------------------------------------------------- ;-- Port Declarations ;--------------------------------------------------------------------- .EQU BUTTONS = 0x55 ;--------------------------------------------------------------------- ;-- Data Definitions ;--------------------------------------------------------------------- .CSEG .ORG 0x01 debounce: IN r0, BUTTONS ;read in buttons TEST r0, 0x01 ;see if button is asserted BREQ debounce BRN delay ;if asserted, go to delay TEST r0, 0x01 ;is btn still asserted after delay BREQ debounce BRN xxx ;act upon btn press delay: MOV r5, 0xFF ;wait state to account for bouncing loop: SUB r5, 0x01 BRNE loop RET

7. We refer to computer languages such as C and Java as being "portable". Define this term in your own words; be sure to reference the role of assembly languages in your answer.

A portable computer language means that you can write this language for any architecture without knowing anything about the underlying assembly language.

5. Describe a situation in a computer architecture where you would require a three-port RAM (reads three addresses, writes one); support your answer with an example assembly language instruction (that you make up) that would require a three-port RAM.

A situation in a computer architecture where you would require a three-port RAM would be if you wanted to add values from three different registers and write the total back into the RAM. ADD R1, R2, R3 R1 ← R2 + R3 + R1

8. How would you change the timer-counter module such that you could use it to "time" the length of time a given signal is asserted. Briefly but completely explain. HINT: The answer for this problem is not along the lines of keeping track of the number of generated interrupts

Add an output so that you can read the value of the timer's count. That way you can start the timer when the signal is asserted and then when the signals is no longer asserted, read the output of the timer counter to get the time.

1. Briefly but completely explain why, in general, why is it important to keep your ISRs as short as possible.

An ISR should be as short as possible so that it is less likely that another interrupt will be missed while it is executing. With a long interrupt, we could also end up having an ISR that would take longer to execute than the non-interrupt code, which would cause huge delays.

10. State whether the RAT MCU is a RISC or CISC processor. Support your statement with at least three characteristics regarding those two types of computer architecture.

Has following qualities of RISC (Reduced Instruction Set Computer) type architectures: Same number of clock cycles: all instructions in the RAT MCU executes in two clock cycles: fetch and execute Simple instructions: only simple arithmetic operations, logical bit operations, storage, program control, I/O, and a few others; each of which only accomplish one basic task Large register file: 32 register spaces instead of a CISC type architecture, which would have something like 8 register spaces

5. The five RAT MCU instruction formats contain different fields for different instructions. In the context of the different instruction formats, briefly describe how it is possible for the same sets of bits to satisfy these different field requirements.

It is possible for the same sets of bits to satisfy these different field requirements because the first five bits will determine what type of instruction format is being read and will then be able to determine what to do with the rest of the bits.

4. What is the minimum execution time an ISR requires? This is the time from when the MCU switches to the interrupt state to when the processor begins executing the next intended instruction, which was scheduled to be executed before the interrupt processing started. Provide a concise answer with adequate description. Assume the interrupts return from the ISR in the disabled state. Recall that that the shortest possible ISR is what you should consider for this problem, which would simply be a RETID instruction.

It takes 5 clock cycles to go through the ISR, which requires the following: Interrupt state, fetch 0x3FF, execute 0x3FF, Fetch ISR, and Execute ISR.

3. Briefly describe what (or who) determines the number of instruction formats a given instruction set contains.

It's completely arbitrary, determined entirely by the designer of the instruction set

11. Describe the difference between the level and pulse outputs of the debounced one-shot module.

Level outputs of a debounced one-shot module keep the output high, whereas the pulse output of a debounced one-shot module outputs the value high only for one clock cycle and then turns it off.

7. Write an assembly language subroutine that would implement an ADDC instruction functionality but without using the ADDC instruction. For this problem, add the two 8-bit unsigned values in register r0 & r1; store the result of this calculation registers r31 & r30, where r31 is the most significant byte. Thus, the r31 & r30 pair represents a valid 9-bit result using the 16 bits in the two registers.

MY_SUB: INIT: MOV r30, r0 ; initialize r30 with r0's value MOV r31, 0x00 ; clear r31 ADD: ADD r30, r1 ; add r30 (= r0) and r1, store in r30 BRCS ADD1 ; if C = 1, then branch to ADD1 RET ; return if C = 0 (r31 = 0x00) ADD1: ADD r31, 0x01 ; add carry to r31 RET ; return

2. Briefly but completely state and explain in your own words the two main aspects of the modern digital design paradigm.

Modern digital design is hierarchical and modular. Modern digital design is hierarchical in that we studied gates rather than the underlying transistors that implemented them, and we extended this approach with slightly more complicated circuit components such as MUXes and decoders, which were a special assembly of gates. Modern digital design is also modular, in that we use block-level designs in which we do not have to redefine core digital devices such as a MUX at the gate level (in other words, we do not have to "reinvent the wheel").

4. In terms of an executing computer program, briefly describe why the FROM_IMMED input is associated with branch and-type instructions and why FROM_STACK is associated with return-type instructions. You will need to consult the assembler manual for this question.

The FROM_IMMED input is associated with branch type instructions because it allows you to load a value immediately from the PC. The FROM_STACK is associated with return type instructions because when a subroutine is called, it stores where the stack pointer is at so that when the subroutine is finished, it can return back to where the instruction came from.

5. Briefly but completely explain how using the "clock prescaler" will prevent the firmware programmer from blinking the LED at all possible frequencies lower than the system clock frequency. For this problem, assume the timer-counter module uses the system clock.

The LEDs are prevented from being blinked at lower frequencies than the system clock because the clock prescaler sets the frequency to the multiplicand of the system clock and a natural number. Thus, the frequency can only be 1*system clock or greater.

3. This experiment implements the C and Z flags as flip-flops. Briefly describe why the RAT MCU architecture requires that these two flip-flops have different control features.

The RAT MCU architecture requires that these two flip-flops have different control features because the C flag has two instructions that the Z flag does not which require two extra signals.. CLC, which clears the carry flag, requires an extra clear signal. SEC, which sets the carry flag, requires an extra set signal.

2. List the differences between a RETIE instruction and a RET instruction.

The RETIE instruction returns from the interrupt with interrupts enabled and the shadow C and Z flags overwrite the C and Z flags. The RET instruction returns from a subroutine without affecting the current C and Z flags.

3. The TEST instruction is massively useful as it allows you to do certain functions using fewer instructions. If the TEST instruction did not exist, show the RAT instructions that would be required to perform the same operation as the TEST instruction.

The TEST instruction performs a bit-wise logical AND operation between the source and destination operands, but does not write the result back to the destination operand. PUSH r1 ; saving the r1 value AND r1, r2 ;AND operation POP r1 ; writing back the original values of r1 and r2

5. For the RAT MCU, there is only one state associated with the interrupt cycle, which means there is only one associated clock cycle. Briefly but completely describe in general what dictates how many states (or clock cycles) a given MCU requires for the interrupt cycle. Once again, for this question, consider "states" and "clock cycles" as the same thing.

The amount of things that need to be done to support the interrupt architecture determines how many clock cycles an MCU requires for the interrupt cycle.

8. Briefly but completely explain how you can disassemble the machine code without the presence of text-based label. Specifically, branch instructions seem to rely on labels in the assembly code; how then can you successfully disassemble a program without the original labels.

The assembler gets rid of the labels and turns them into numbers (the addresses of memory in which the instruction corresponding to that label is stored), therefore we always disassemble a program without the original labels because the assembler got rid of them.

7. Briefly describe the general purpose of the assembly language listing file.

The assembly language listing file shows the source code, the object code to which it is translated, and additional information. Examination of the listing file can help you understand the assembly process. When your source file contains errors, this .LST file displays error messages at the points of error, helping to locate the offending statements.

9. What would be the capacity of the prog_rom if you kept the number of storage locations the same but increased the size of each instruction from 18 to 24 bits? Show your calculations for this question.

The capacity of the prog_rom would be 24576 bits if you kept the number of storage locations the same but increased the size of each instruction from 18 to 24 bits. 210 x 24 1024 x 24 = 24576 bits

7. The timer-counter provided for this experiment provided a means to easily blink an LED with a 50% duty cycle. Using the RAT MCU and the timer-counter, there is a programming "overhead" associated with blinking the LED at an exact frequency if the duty cycle is not 50%. Briefly describe how and when this overhead can interfere with the frequency output of the blinking LED.

The code that is written to handle the different duty cycle takes some amount of time to execute. The time taken up by that code delays the LED blinking causing it to not be exact.

3. Examine the VHDL model for the timer-counter and briefly but completely describe how it operates. Be sure to mention both the counter portion as well as the pre-scaler.

The counter portion of the timer-counter module operates similarly to a counter in the sense that it counts upward when enabled starting from zero until it reaches its terminal count, resets to zero, and counts upward again. However, the main difference is that this module outputs a pulse when its count is equivalent to the count in the TCCNTx registers (which are three 8-bit registers hold the terminal counts). The duration of the output pulse is two system clock periods. The prescaler portion of the timer counter module is controlled by a 4-bit signal that prescales the clock input to the timer counter. It gives the user the ability to reduce the input clock frequency. The prescale bits take effect when the timer counter reaches the current prescale value.

8. Briefly but completely describe the major problem with the RAT MCU receiving an interrupt while it is in the act of processing an interrupt. For this problem, consider the interrupts as being unmasked when the MCU receives the interrupt.

The major problem with the RAT MCU receiving an interrupt with the interrupts unmasked while it is in the act of processing an interrupt, is that the C and Z flags will get overwritten and context will be lost. In addition, the address of the instruction will be pushed to the stack which is in the ISR.

11. For the following code fragment, what is the minimum value for "?????" to make the program happy? ;---------------------------------------------------------------- ;--.DB Directives ;---------------------------------------------------------------- .DSEG ; we're in the data segment .ORG 0xC0 Roof: Floor: .DB 0x50, 0x61, 0x82, 0x33 .DB 0x35, 0x36, 0x37, 0x38, 0x39, 0x4A, 0x3F Wall: .DB 0xAA, 0xBB, 0xCC, 0xDD, 0x39, 0x4A, 0x4C, 0x3E .CSEG .ORG ????? Main: BRN Main

The minimum value for .ORG would be 0x27.

1. The prog_rom.vhd file in this experiment models a synchronous circuit. Briefly describe what the notion of synchronous means in the context of this ROM.

The prog rom reads on the clock edge

1. Briefly but completely describe how the provided program verified the proper operation of the shadow C & Z flags.

The provided program first clears both C and Z flags. Upon interrupt, it copies the flags into the shadow C and Z flags. During the interrupt, it sets both flags. When the instruction RETIE is executed, it returns what was initially loaded into the shadow flags back to the C and Z flags.

1. Briefly describe why it is "more efficient" to use a timer-counter peripheral to blink an LED and using a dumb loop (delay loop) to blink an LED.

The time-counter uses an interrupt to blink the LED, which means that it is run as a background task, enabling us to run a foreground task with more processing power. If we use a delay loop, then all of the processing power will be focused on blinking the LED, using more of the system's processing power than if it was a background task.

10. Briefly describe why there is no need for instructions that do nothing other than alter the value of the Z flag.

There is no need for instructions that do nothing but alter the Z flag because the Z flag is never shifted into a register by an instruction.

9. The previous two questions were clever, but not realistic. Briefly describe why are these problems not 100% doable in real life.

These problems are not 100% doable in real life because since it is a subroutine, the CALL instruction would need to store the address it is currently at in order to RET back to it. However, by initializing all locations of the the scratch RAM through this subroutine, you have just overwritten the address you wanted to save.

9. Remember those setup and hold times? Whatever happened to those? Is this something we should be worried about in this Experiment? Briefly explain.

They are still important, if the clock speed is too fast, complications when writing to the REG_FILE (). However, the Register's setup and hold time requirements are much faster than the the ROM and RAM access times, which means the ROM or RAM will probably act as a bottleneck before we need to worry about setup and hold times.

4. This experiment asked you to include only the control signals that a particular instruction used regardless of whether they were previously scheduled to be assigned to zero(s). Briefly state why this approach represents excellent VHDL coding style.

This approach represents excellent VHDL coding style because by scheduling all the signals for a particular instruction regardless if they were already previously assigned, you can easily and clearly see what each particular instruction does as well aids with debugging.

4. Interrupt architectures generally always automatically mask interrupts upon receiving an interrupt. Briefly but completely describe why this is a good approach, and a better approach than attempting to rely masking the interrupts under program control.

This is a good approach because the return to Program Counter is a branch command and if the interrupt is constantly unmasked, the path would continue calling the ISR subroutine.

6. Nested subroutines are quite common in assembly language programming. Accordingly, there is also the notion of nested interrupts. Briefly explain how you could allow nested interrupts to occur under program control on the RAT MCU. For this problem, don't worry about the issues with the C and Z flags.

To allow for nested interrupts, we would add an SEI instruction to the very beginning of the ISR, enabling other interrupts to be branched to during that interrupt.

6. In assembly language-land, we refer to instructions that do nothing as "nops" (pronounced "know ops"). In academia, we refer to "nops" as administrators. Many assembly language instructions actually have a dedicated nop instruction, but the RAT MCU does not. There are two approaches to faking a nop instruction in VHDL using the existing RAT MCU instruction set. For this questions, list those two approaches. HINT: one of these approaches involves a branch instruction.

Two approaches to faking a nop instruction in VHDL would be: Using a MOV on the same register. (MOV r1, r1) Using a BRN instruction to branch to the very next instruction.

6. You can typically use assembly language to make a given program written in a higher level language run faster. Briefly but fully explain this concept.

We can create a more efficient code than a compiler would.

5. How much memory does the control unit use in this experiment contain? Also, state which signal represents that memory.

We know that the control unit in this experiment contains at least 2 bits of memory because it has 3 states, but we can't know exactly how much it has. The signal that represents this memory is the PS signal.

3. If the dual-port RAM you used in this experiment could store two different values at the same time, could you implement this circuit in a fewer number of states? Relate your answer to the state diagram for this experiment and support your answer with intelligent commentary.

Yes, we could use fewer states with a dual-port RAM because we no longer need two states to input data into registers A and B separately, we could use just one and input data simultaneously.

10. Is it possible to have two or more labels in an assembly language program with the same numerical value? Briefly but completely explain.

A numerical label can be reused because there can be more than one label referring to the same set of instructions.

10. Write a RAT assembly language subroutine that swaps the values in two different registers without accessing memory or changing the value in any register other than the two registers in question. Use only shift type instructions

swap: CLC LSL r0 ; C = r0[7], r0 LSB = 0 LSL r1 ; C = r1[7], r1 LSB = r0[7] LSL r0 ; C = r0[6], r0 LSB = r1[7] LSL r1 ; C = r0[6], r1 LSB = r0[6] LSL r0 ; C = r0[5], r0 LSB = r1[6] LSL r1 ; C = r0[5], r1 LSB = r0[5] LSL r0 ; C = r0[4], r0 LSB = r1[5] LSL r1 ; C = r0[4], r1 LSB = r0[4] LSL r0 ; C = r0[3], r0 LSB = r1[4] LSL r1 ; C = r0[3], r1 LSB = r0[3] LSL r0 ; C = r0[2], r0 LSB = r1[3] LSL r1 ; C = r0[2], r1 LSB = r0[2] LSL r0 ; C = r0[1], r0 LSB = r1[2] LSL r1 ; C = r0[1], r1 LSB = r0[1] LSL r0 ; C = r0[0], r0 LSB = r1[1] LSL r1 ; C = r0[0], r1 LSB = r0[0] LSL r0 ; C = r0[0, original carry], r0 LSB = r1[0] return: RET ; returns subroutine

8. Briefly describe the differences in how the control unit code handles 5-bit opcodes as opposed to 7-bit opcodes.

As shown below, the control unit code handles 5-bit opcodes by listing all of the possibilities of the same 5-bit combination and assigning it to the same instruction. Since 5-bit opcodes do not care about the last two bits, all of the opcodes below should produce the same result. -- IN reg-immed ------ when "1100100" | "1100101" | "1100110" | "1100111" => RF_WR_SEL <= "11"; RF_WR <= '1'; In contrast, for 7-bit opcodes the control unit code assigns each one individually to their own signals as shown below. This will take into account all 7-bits of the 7-bit opcode and will differentiate between the different instructions. -- BRN ------------------- when "0010000" => PC_MUX_SEL <= "00"; PC_LD <= '1';

5. List two instructions from the RAT instruction set that would use the PC's "FROM_IMMED" input. You will need to consult the RAT MCU Assembler Manual for this question. In particular, examine the RTL associated with each instruction.

BRN and CALL would use the PC's "FROM_IMMED" input.

3. Based on the state diagram in Figure 21, would it be possible to assert the interrupt signal and not enter into an interrupt cycle? Briefly but completely explain. Assume the interrupt is unmasked.

Based on the state diagram in Figure 21, it is possible to assert the interrupt signal and not enter into an interrupt cycle if and only if it is not currently on the execute state. If it is on the execute state and the interrupt signal is asserted, it will enter into an interrupt cycle.

2. We often consider the ISR code as having a "higher priority" than the non-interrupt code. Briefly but fully explain this concept.

Being higher priority means that if an interrupt occurs at the same time that non-interrupt code is supposed to be executed, the program will branch to the ISR instead of the non-interrupt code.

13. Briefly but completely discuss the advantages, if any, of implementing the stack and generic storage RAM as separate modules.

By having a separate stack and storage RAM, we don't run the risk of overwriting data. When we combine the stack and storage RAM, it is possible to overwrite data.

2. The timer-counter module uses a "clock pre-scaler". Briefly describe how you would model the timer-counter without the pre-scaler yet still be able to attain approximately the same blink rates as with the prescaler.

By increasing the bit width of the terminal count register, it is possible to effectively get the same blink rates while still using the prescaler.

6. Provide a diagram of a digital circuit that you could use to model a 4x10 RAM using four ten-bit registers and some supporting circuitry. For this problem, consider the registers to have "chip selects" that turn on the RAMs. Note that when the RAM is turned on, it drives a common output bus shared by all the RAMs. Don't use a MUX in your solution.

refer to google docs

1. Semiconductor memory has three types of signals. State these signal types and briefly describe each one.

Data - Information in the address being input or output from the register Address - Memory location in the structure Control - Determine and direct the instructions associated with memory

1. The PC has two types of input signals: control signals and data signals, where we consider the clock input a type of control signal. List which inputs are data inputs and which are control inputs. For this problem, use the "PC" as it appears in Figure 7.

Data Inputs: FROM_IMMED, FROM_STACK Control Inputs: PC_MUX_SEL, PC_LD, PC_INC, RST, CLK

7. Limiting the number of states in the design forces you to create a "generic" design, which roughly means you "reused" some states in your FSM as it completed the assigned task in this experiment. Briefly but completely explain the main benefit of implementing this particular style of generic design in the FSM. One of the constraints of the FSM in this experiment was to make the FSM such that if the length of the sequence changed, the FSM would still work. This question does not refer to that type of genericity.

Each state is represented by a binary value stored in flip-flops. For a given number of states, the number of flip-flops required equals (ceiling function) log 2 of the number of states

4. In general, adding new instructions to an instruction set requires that you also provide extra hardware to support that instruction. Did adding instructions such as TEST or CMP increase the amount of hardware required by the RAT ALU architecture. Support your answer with brief but adequate explanation; make sure you can back your answer with actual evidence.

For these instructions, there was no extra hardware required, as both these use the same hardware as the AND or SUB instructions, but they do not write the result back into the register. Therefore, we hope that the RAT MCU was smart enough to utilize the existing hardware for these operations, however we do not know for sure whether it utilized the existing hardware or not.

12. Briefly but completely describe the changes to the RAT MCU architecture required if you were to implement the stack and data storage RAM as separate modules; draw a schematic to help describe your approach.

refer to picture in google doc

7. Briefly but completely describe the major problem with the RAT MCU receiving an interrupt while it is in the act of processing an interrupt. For this problem, consider the interrupts as being masked when the MCU receives the interrupt.

If processing an interrupt takes too long and the interrupts are masked, the RAT MCU will not detect any intermediate interrupts between receiving the interrupt and finishing the interrupt process. This can make the hardware less responsive.

10. If the prog_rom increased from 1k x 18 to 4k x 24, what would be the total bit capacity and how many addresses lines would be required for the device? Show your calculations for this question.

If the prog_rom increased from 1k x 18 to 4k x 24, the total bit capacity would be 98304 and the device would require 12 address lines. 212 x 24 4096 x 24 = 98304 bits

5. In this lab activity, you implemented the stack pointer as a counter. Provide a diagram of the supporting hardware if you had to implement the stack pointer as a loadable register.

If the stack pointer was a loadable register, we would need to add a MUX connected to the B input of an RCA that is connected to another MUX that is connected to the DATA_IN input of the SP. Instead of the control unit outputting the SP_INCR and SP_DECR, the control unit would output a select signal to the MUX connected to the input of the RCA to decide between adding 1 (incrementing) or -1 (decrementing) to the stack pointer value. The MUX connected to the DATA_IN input to the SP has the options of either inputting the RCA result into the DATA_IN or inputting the DX_OUT ouput from the Register File into the DATA_IN. The SP_LD signal from the Control Unit is still required.

6. Changing frequencies of the timer-counter can possibly create a timing error for one clock period. Briefly describe what causes this one hiccup.

If we change the TCNTx numbers during a clock cycle, then the clock cycle may count up to the new values instead of the values set at the beginning of the clock cycle. This would cause the cycle to end at the wrong time.

5. Consider a Moore-type FSM output; if an output becomes asserted when it enters a given state, what is the soonest that output could take effect for an external hardware module? For this problem, assume the external hardware module is synchronous and shares the same clock as the FSM. Also, assume the FSM and external module are both RET devices.

In a Moore FSM, the soonest the output could take effect is on the following clock cycle.

5. The RAT MCU uses the TEST and AND instructions for bit masking. Describe how you would implement an AND-type bit masking using the RAT MCU instruction set but without using the TEST or AND instruction. For this problem, you need to "clear bits" using the OR instruction.

In order to clear bits without AND, you would need to first set them by using OR with 1, then toggle the bits by using EXOR with 1.

8. Relative the previous problem, how would I modify the hardware to have either the X value or Y value act as an address to the scratch RAM. For this problem, your RAT MCU hardware should not have anything "bigger" than a 4:1 MUX.

In order to modify the hardware to have either the X value or Y value act as an address to the scratch RAM, you would need to add a 2:1 MUX with the inputs being the X and Y values of the scratch RAM, and its output connected to the 0 address of the MUX leading to the address input of the scratch RAM. This would allow you to select from the X or Y output.

7. In theory, how deep could you nest interrupts on the RAT MCU? Briefly but concisely explain.

In theory, interrupts can be nested for as many times as the size of the Scratch RAM in the MCU, or the stack. Since each ISR call pushes the next PC count onto the stack, when the stack runs out of space, the hardware will break or have an error or whatever would happen as a result of a stack overflow. Any amount of nested interrupts up to this point will ensure proper operation.

1. Briefly explain why was it is not problematic to ignore the bounce issues associated with the button in this experiment?

In this experiment, the clock cycle is much slower than the length of time the button bounces, so by the time the clock edge occurs, the button output will be stable.

6. We generally consider interrupts "asynchronous" in nature. However, looking at Figure 21, the interrupts appear to be synchronous. Briefly describe what it means for the interrupts to be asynchronous and why it is that they don't appear asynchronous in Figure 21.

Interrupts are asynchronous because they can occur at any time during a clock cycle. The interrupts appear to be synchronous because in order for the interrupt cycle to be entered, at the end of the execute cycle, INT needs to be asserted.

3. Suddenly, your boss wants to use a different prog_rom: instead of one 1024x18, she want to use two 512x18 ROMs. Show the circuit that you would need to make this work. This circuit should contain two ROMs, the same 10-bit PC, and whatever other circuitry you need to make the circuit function properly. Draw a schematic of your solution.

check google drive