Chapter 14: Sequential Logic

Equivalent States

Two states that have the same output, and the same next state for the same input values.

One-Hot Encoding

Uses N bits for N states, with each encoding having exactly one bit set to 1. A one-hot encoding uses more bits and thus a larger state register than a binary encoding, but may yield fewer gates, especially for relatively few states.

Binary Encoding

Uses the fewest bits possible for a given number of states. Ex: 2 bits for 4 states, or 3 bits for 8 states.

Moore

Action appears in an FSM's state, as in the FSMs seen in earlier sections.

Mealy

Action appears on an FSM's transition.

Controller

An FSM can be converted to a sequential circuit.

Design

Converting behavior (like an FSM) to a circuit (like a controller).

Analysis

Converting from a circuit to behavior (like an FSM).

Level to Pulse Converter

Converts a longer-than-one-cycle input pulse to a one-cycle output pulse. When that output is then input to other systems, a one-cycle pulse can simplify those systems' FSMs.

Output Encoding

If each state has a unique output value combination, then those output values may also be used for the state encoding.

A Circuit is Sequential

If the circuit's output values depend not only on the present input values, but also on the sequence of past values.

A Circuit is Combinational

If the circuit's output values depend solely on the present combination of input values.

Register

Is a circuit that stores a group of bits; a 3-bit register stores three bits.

FSM (Finite State Machine)

Is a computation model capable of describing sequential behavior.

Asynchronous Input

Is an input that is not synchronized with a circuit's clock.

Metastable State

Is in a state other than a stable 0 or a stable 1. A flip-flop in a metastable state can have a voltage that is a value between 0 and 1, and that voltage may oscillate.

Pulse

Is the changing of a signal from 0 to 1 and back to 0.

Clock Frequency

Is the cycles per second, in units of hertz (Hz) meaning cycles/second. Ex: A 1 MHz clock has 1 million cycles per second. Frequency is the inverse of period. Ex: A 1 microsecond (0.000001) period yields a frequency of 1 MHz (because 1 / 0.000001 s = 1,000,000 Hz).

Clock Frequency

Is the inverse of the clock's period: 1 / (clock period).

State

Is the present "situation" of a digital system, akin to a person's state being sleeping, eating, or working.

State Register

Is the register in a controller, holding an FSM's present state. Each state requires a unique bit encoding, which is then stored in the state register. Three or four states require 2 bits (00, 01, 10, 11). Five, six, seven, or eight states require 3 bits (000, 001, ..., 111). N states require log2N bits.

Clock Cycle

Is the time between two rising edges, that time being the clock period.

Hold Time

Is time the input of a flip-flop must be stable after a clock edge.

Setup Time

Is time the input of a flip-flop must be stable before a clock edge.

Capture Behavior

Means for a designer to describe desired behavior in some form. Designers commonly use an FSM to capture sequential behavior.

Oscillate

Means to change from 0 to 1 to 0 to 1 repeatedly. Due to different gate and wire delays, eventually the latch will settle into a stored 0 or 1, but which one is unknown.

Sequential Curcuit's

Output is dependent on the present and the past sequence of input values, which necessarily means the circuit stores at least one bit. In contrast, a combinational circuit's output is dependent only on the present combination of input values.

Button De Bouncer

Outputs a single pulse when a button is pressed, ignoring the multiple small pulses (bounces) that may occur due to a button's mechanical imperfections.

Latch

Stores a new bit while an enable input is 1. A latch is said to be level sensitive, storing when the enable's "level" is high. In contrast, a flip-flop stores a new bit only at the instant of clock input's rising edge. A flip-flop is said to be edge-triggered.

D Latch

Stores one bit, with an input d having the bit to be stored, an input e that when 1 enables storing the bit, and with the stored bit appearing on output q. D and d are short for "data", and e for "enable".

SR Latch

Stores one bit, with an input s to set the latch to 1, an input r to reset the latch to 0, and with the stored bit appearing on output q. S and s are for "set", and R and r for "reset".

Loading

Storing bits in a register.

Critical Path

The clock's period must be longer than the longest delay from the state register's output to the state register's input.

Rising Edge

The instant a clock signal changes from 0 to 1.

Partitioning Method

The method first groups states per output values; states with different output values cannot be equivalent. Then, for each state in a group, the method checks next states' groups; if different, those states cannot be equivalent and the group is split. The method continues checking every group, until no group was split.

Latch

The simplest circuit for storing a bit.