Computer Organization and Architecture
Convert base 10 to any base.
"Price is Right"
What is the integer range of a quad word?
0 to 2^64 minus 1
What is the integer range of an unsigned word?
0 to 65,535
This ARM mode of operation implements virtual memory or memory protection.
Abort (abt)
This Intel x86 Instruction Type allows performance of mathematical operations (ADD, SUB, MUL, and DIV).
Arithmetic
This ARM instruction type handles data-processing of miscellaneous instructions to include arithmetic and logical operations (ADD & ROR).
Arithmetic and Logic add r0, #16
What are two common types of image formats?
BMP - Bitmap PNG - Portable Network Graphics
This Intel x86 Segment Register points to the code.
Code Segment (CS)
Analog is what type of signal?
Continuous
When set, this determines if the interface will send or receive.
Control Port
This ARM instruction type handles branch, branch with link, and block data transfer instructions to allow for control transfer, such as a branch or call to a subroutine.
Control Transfer
This type of bus arbitration passes bus access from highest to lowest priority device.
Daisy Chain
This segment holds data defined within the code.
Data Segment
This allows for a reduction in data size so that data can be stored or transmitted more efficiently.
Data compression
This bus line is dedicated to transferring data.
Data line
This Intel x86 General Purpose Registry is the destination pointer for string operations.
Destination (DI)
This provides a physical way for the peripheral devices to interface with a computer.
Device interface A device interface consists of at least three registers; control, data, and status. These registers are referred to as ports.
A "Rotation" is used for what?
Encryption Ex: ABCDEF CDEFGH
This Intel x86 Segment Register points to the extra data in a tiered approach.
Extra Segment (ES)
This Intel x86 Segment Register is used after Extra Segment (ES)
F Segment (FS)
This ARM mode of operation is the fast interrupt for high-speed transfer.
FIQ (fiq)
True or false? ARM instructions have a fixed 64-bit length.
False ARM instructions have a fixed 32-bit length.
True or False? Intel x86 64-bit computer systems can not operate in compatibility mode and 64-bit mode.
False - They can operate in compatibility mode. Compatibility mode allows most 16 and 32 bit programs to execute without being modified for 64 bit operations.
True or false? Computers add and subtract binary.
False, computers can only add, which is why we use 2's complement. 2's complement is performed when and only when you are expressing a negative number, which can then be recognized by a computer. Remember: Convert to binary, inverse if negative, add 1 and done. Inverse and add 1 again to find magnitude of negative 2's complement, and don't forget to replace the sign!
This Intel x86 Instruction Type has the ability to set and clear a flag bit when used with ADD and SUB instructions where there are carries.
Flag The flag would indicate a carry
This Intel x86 Data Type allows for fractions.
Floating-point
This Intel x86 Instruction Type allows mathematical operations on floating-point data types.
Floating-point
This connects the processor to Northbridge.
Front-side bus
This ARM Data Type when accessed from memory is in the following sizes: Byte (8-bit), halfword (16-bit), word (32-bit), double word (64-bit).
Fundamental
This Intel x86 Data Type deals with fundamental base data types (unsigned integers).
Fundamental
This Intel x86 Segment Register is used after F Segment (FS)
G Segment (GS)
What are the four basic program execution registers for the CISC?
GPR's (General Purpose Registers), Segment Registers, Program status and Control Registers, and Instruction Pointer Registers.
This Intel x86 Operand Addressing Mode directly addresses an I/O device.
I/O Port
This interfaces with the processor, memory, and one or more peripheral devices. Similar to a CPU, but for only one purpose and may or may not include its own memory.
I/O module (Hardware or software)
This Intel x86 Operand Addressing Mode value is in the instruction.
Immediate
This operand value is present in the instruction.
Immediate
This is the effective address of operand generated by adding value in address field (Immediate) and contents of register (REG).
Indexed or based
This operand value is found by looking to the contents of the Direct value.
Indirect Immediate -> Direct -> Indirect
This ARM Register holds the current instruction address.
Instruction Pointer Register Program Counter (R15 or PC)
This three digit SPR is used by the decoder to decode the instruction.
Instruction Register (IR)
In a CISC processor architecture, this is an interface that allows all software to run on hardware
Instruction Set Architecture (ISA) Process architecture looks at the behavior of the processor in regards to the logic and implementation seen by the programmer: data types, instruction types, operand addressing, and modes of operation.
This Intel x86 Instruction Type performs logical operations (AND, OR XOR, and NOT).
Logical
This is used to connect slow data rate devices such as the Basic Input/Output System (BIOS) that is used to start a computer system, keyboard, and mouse.
Low Pin Count (LPC) Bus
This two digit SPR is used to point to the correct memory address to read or write.
Memory Address Register (MAR)
This Intel x86 Register reports the status of the program being executed, and can be used to detect stack overflows.
Program Status and Control Register (FLAGS)
What are the four I/O control methods?
Programmed I/O, Interrupt-driven I/O, Memory-mapped I/O, and Direct Memory Access (DMA)
The amount of pixels determines what?
Resolution, measured in megapixels (MP)
ROT stands for what?
Rotate by places Ex: ROT13, a substitution cipher produced by rotating plaintext right 13 letters of the 26 letter Latin alphabet.
This ARM instruction type handles media instructions that perform operations in parallel, such as the ADD operation multiple times, concurrently.
SIMD
This ARM mode of operation is used to transfer control from non-secure to secure and vice versa by the processor.
Secure Monitor (mon)
What is a sequence of instructions written to perform a specified computer task.
Software
This Intel x86 Segment Register points to the stack.
Stack Segment (SS)
This obtains information such as "printer out of paper, don't send any more data", or, for a serial transmission, "all the bis of the data element haven't yet been received".
Status Port
This Intel x86 Instruction Type fixes problems with MMX to achieve better results and also works on floating-point data types by streaming MMX.
Streaming SIMD Extension (SSE)
This segment of code within a program is used to perform a specific task that is relatively independent of the rest of the program.
Subroutine In order for a subroutine to work, it is necessary to have a data structure called a stack, which saves the state of the caller's program.
This ARM mode of operation is the protected mode for the OS.
Supervisor (svc)
This ARM mode of operation runs privileged operating system (OS) tasks.
System (sys)
Kilo (kB/kHz)
Thousand Storage: 2^10 - 1,024 Speed/Time: 10^3 - 1,000
Tera (TB/THz)
Trillion Storage: 2^40 - 1,099,511,627,776 Speed/Time: 10^3 - 1,000,000,000,000
True or false? ARM operand addressing modes are a method for generating the memory address used by a load or store instruction.
True
This is connected to the Southbridge. (great explaination, eh?...)
Universal Serial Bus (USB)
This ARM mode of operation is the user mode mode, and is the usual ARM program execution state. It's also used for executing most application programs.
User (Usr)
What are two common types of audio formats?
WAV - Waveform Audio File Format. MP3 - Moving Picture Experts Group version 1 Audio Layer-3
ZIP compression format is used with what OS?
Windows
What is a tangible computer component?
Hardware
What is a bit?
A bit is a place holder in a base two numbering system, allowing 1 or 0, and representing On or Off respectively.
This Intel x86 Instruction Type moves data between registers and memory (MOV).
Data Transfer
This ARM instruction type handles load/store and unsigned byte instructions to transfer data to and from memory and register.
Data Transfer ldr r0, [r1]
The LMC uses two types of registers, what are they?
General Purpose Register (GPR) used for any purpose, and Special Purpose Register (SPR) which are used for one singular purpose.
What is the name of the 16 bit IEEE (Institute of Electrical and Electronics Engineers) 754 floating-point standard?
Half-Precision Sign: (1-neg, 0-pos) Exponent: (5 bits) Add or subtract from 15 (Range: -14, 15) Significand: (10 bits) All bits right of decimal after moving decimal to right of furthest most 1.
This ARM mode of operation is used for general-purpose interrupt handling.
IRQ (irq)
This connects main memory to Northbridge.
Memory bus
What is a 4 bit grouping called?
Nibble
This power is used for computer system data storage.
Power of 2
How is little endian stored?
Right to left. Little endian is used by Intel x86 0x03 0x02 0x01 0x00
This Intel x86 Data Type deals with multiple bits or bytes; better known as bit string and byte string.
String A byte string can be used to hold the ASCII in memory.
This Intel x86 Instruction Type allows movement of whole strings to and from memory.
String Strings are groups of characters where characters are letters and numbers.
True or False? RISC uses a load/store architecture.
True The data processing operation is only performed in a register and NEVER directly in the memory.
GZIP compression format is used with what OS?
Unix
ARM has how many General Purpose Registers?
13- R0 through R12
Unicode is made up of how many bits and represents what language(s)?
16 bits (first 8 bits still in ASCII format) With Unicode being 16 bits and having 65,536 possible characters, Unicode can represent all the languages of the world.
What ASCII hexadecimal characters represent uppercase A and lowercase a?
41= Capital A 61= lowercase a
The LMC utilizes how many registers?
5 - The Accumulator, Program Counter, Instruction Register, Memory Address Register, and Memory Data Register
Digital is what type of signal?
A sequence of discrete values
The Little Man Computer (LMC) is developed for what?
A simplified training model that represents the way computers work.
What is run-length encoding (RLE)?
A type of data compression where runs of any length are represented by three characters @e7. @ denotes the following character 3 was repeated 7 times. ddeeeeeeeff dd@e7ff
What are the two most popular ways to represent text in Decimal and Hexadecimal?
ASCII and Unicode
This Intel x86 General Purpose Registry is used with the accumulator for arithmetic and logical operation.
Accumulator (AX)
This bus line indicates where location data should be read from or written to.
Address line
A bus is broken out into what three lines?
Address, data, and control line.
This is an example of a RISC based architecture.
Advanced RISC Machine (RISC)
This Intel x86 Operand Addressing Mode allows assembler or compiler to encode a customized addressing mode.
Assembler and Compiler
What is a low-level programming language for computers where each statement corresponds to a single machine language instruction, but is more readable than the bits themselves.
Assembly Language
This Intel x86 General Purpose Registry is the base pointer to the data segment.
Base (BX)
This Intel x86 Instruction Type allows the movement of bits within a string (SHR, SAL, SAR, SHL, ROR, and ROL).
Bit Manipulation
This Intel x86 Data Type contains bits that can be employed for Boolean values. Where 1 is true and 0 is false, it allows for conditional statements.
Bit field
This allows for communication of dissimilar buses since buses talk in different languages and speeds.
Bridge "The interpreter"
This is the act of storing data in a region of physical memory, and is used to temporarily hold data while it is being moved from one place to another.
Buffering
This is a system for resolving bus control conflicts and assigning priorities to request for bus control in a system where there is more than one master.
Bus arbitration
What is an 8 bit grouping called?
Byte
When this subroutine is executed, the address of the next instruction is saved to the stack (PC+1) and PC points to the beginning of the subroutine.
CAL CAL is the Op Code, and it will be paired with an Operand (ex: CAL | 28) ***Important: CAL Procedure*** 1. PC+1 -> Stack 2. Operand -> PC 3. SP (up arrow) Stack Pointer moves up.
This type of bus arbitration grants bus access on directed control lines from each device to a centralized master.
Centralized parallel
CISC
Complex Instruction Set Computing CISC is a computer with several low-level operations combined into one instruction (Intel x86). Most servers, desktops, and laptops on the market use CISC based processor architecture.
This Intel x86 Instruction Type changes program flow (JMP and JGE).
Control Transfer
This bus line indicates what devices have access to the bus and for what.
Control line Ex: The control line is used for interrupts and synchronization.
This Intel x86 General Purpose Registry is a counter for string and loop operations.
Counter (CX)
This ARM Register provides Program Status and Control.
Current Program Status Register (CPSR) or Application Program Status Register (APSR) hold the status of the last instruction, such as flags. Save Program Status Register (SPSR) is used to save a copy CPSR when switching modes.
This Intel x86 General Purpose Registry is used in I/O operations for data transfer.
Data (DX)
This allows data elements to be transmitted or to hold data elements received.
Data Port
This Intel x86 Segment Register points to the data.
Data Segment (DS)
This operand value is the effective address of the operand in the address field (where the immediate value points).
Direct
This connects Northbridge and to Southbridge.
Direct Media Interface (DMI)
This type of bus arbitration allows all devices to request access to the bus and when there are collisions, simultaneous requests, the device requests again.
Distributed using collision detection
This type of bus arbitration utilizes priority device between communications between the devices themselves.
Distributed using self-selection
What is a 32 bit grouping called?
Double word
The way data is stored in memory is known as what?
Endian, or byte order.
This ARM instruction type handles Coporcessor instructions and supervisor call instructions that allow transfer of privilege levels and SIMD to include floating-point.
Flag
This is a series of steps to coordinate asynchronous communication in which sender and receiver proceed to the next step only when both parties agree current step was complete.
Handshaking Bus control is active and data memory address is put on the bus line. Memory system puts required data on data line. Data is acknowledged via control line.
This segment holds data of two types; initialized and uninitialized (runtime).
Heap Segment The heap holds blocks that can create variable sized data and uses another data structure called a LINKED LIST, which is used to identify allocated and unallocated blocks.
This Intel x86 Instruction Type moves data to memory or register from an I/O port (IN and OUT).
I/O
What does the LMC use to read data from the user, up to three digits in size, and is also used to write data to the user, also up to three digits in size?
I/O (Input / Output)
This device is a mechanism through which the computer is fed information, such as from a keyboard or mouse , and outputs results of a computation to a user or other computer.
I/O - Input/Output
This ARM operand addressing mode (offset) is an unsigned number that can be added to or subtracted from the base register value.
Immediate Immediate offset addressing is useful for accessing data elements that are a fixed distance from the start of the data object, such as structure fields, stack offsets, and input/output registers.
This Intel x86 Register contains a pointer to the next instruction to be executed.
Instruction Pointer Register (IP) 64 Bit 32 Bit 16 Bit 8 Bit RAX EAX AX AH/AL RBX EBX BX BH/BL RCX ECX CX CH/CL RDX EDX DX DH/DL RBP EBP BP RSI ESI SI RDI EDI DI RSP ESP SP
How is big endian stored?
Left to right. Big endian is used by ARM 0x00 0x01 0x02 0x03
This Intel x86 Instruction Type can be performed on many of the instructions available in other Instruction Types, but is strictly on the Packed SIMD data type.
Matrix Math Extensions (MMX) MMX technology was added to deal with multimedia, but it was found to better serve digital signal processing and graphic processing.
This Intel x86 Operand Addressing Mode is used as a pointer to a memory address.
Memory
This storage area stores running programs, and the data required to keep these programs running?
Memory
This three digit SPR is used to hold data to be read or written to the Accumulator (A) or memory.
Memory Data Register (MDR)
Mega (MB/MHz)
Million Storage: 2^20 - 1,048,576 Speed/Time: 10^6 - 1,000,000
This is a short character sequence that represents instructions for the LMC to execute.
Mnemonics - Mnemonics are a human language that correspond to opcodes, which are a machine language, and are used by humans to input instructions for a computer to perform. When a mnemonic instruction is input into a computer, the computer assembles the corresponding opcode through a process called linking.
ROL - Rotate Left
Moves bits in the binary to the left, then takes each left most bit and inserts it on the right. 74 (unsigned integer) <- (2 bits) 01001010 01001010 <-
ROR - Rotate Right
Moves bits in the binary to the right, then takes each right most bit and inserts on the left. 74 (unsigned integer) 01001010 -> (2 bits) ->10010010
This bus topology connects more than two computers together.
Multi-point Bus
Convert any base to base 10.
Multiply by place power for each digit and add.
Convert fractional numbers less than one to any base.
Multiply the base 10 number by the base you are converting to. Ex: 0.625 base 10 to base 2 0.625 * 2 = 1.25 (each 1 or 0 left of the decimal is used) 0.250 * 2 = 0.50 0.500 * 2 = 1.00 So, 0.625 in base 10 equals .101 in base 2
This has an internal, front-side, memory, and PCI Express buses.
Northbridge
This Intel x86 Data Type allows for mathematical operations to be performed.
Numeric The two sub types are unsigned integers and signed integers (positive and negative integers).
Base Notation
Numeric values represented through increasing powers of a base referred to as a weighted numbering system. Ex: Base 2, Base 8, Base 10, Base 16
This Intel x86 Operand Addressing Mode can be directly specified as a static value called displacement, a base, and index, or scale factor, and one or more can be used at a time.
Offset
Name the Op code and mnemonic equivalent for the machine control function "HALT".
Op Code: 000 Mnemonic: HLT
Name the Op code and mnemonic equivalent for the Arithmetic function "ADD".
Op Code: 1XX Mnemonic: ADD
Name the Op code and mnemonic equivalent for the Arithmetic function "SUBTRACT".
Op Code: 2XX Mnemonic: SUB
This is used as a mechanism, shared by many different instructions, for generating values used by the instructions.
Operand Addressing Modes. (Op Code | Operand)
Once the instruction is copied into the IR from the MDR, it is decoded (D). The execute (E) is dependent on the instruction that is being performed. This is the LMC fetch-decode-execute instruction for HALT (000/HLT).
PC -> MAR MDR -> IR
This is the LMC fetch-decode-execute instruction for OUTPUT (902/OUT).
PC -> MAR MDR -> IR A -> OUT PC+1 -> PC
This is the LMC fetch-decode-execute instruction for Branch on Zero (7XX/BRZ).
PC -> MAR MDR -> IR IF A == 0 THEN IR [ADDR] -> PC ELSE PC+1 -> PC
This is the LMC fetch-decode-execute instruction for Branch on Positive (8XX/BRP).
PC -> MAR MDR -> IR IF A >= 0 THEN IR [ADDR] -> PC ELSE PC+1 -> PC
This is the basic fetch cycle, which retrieves code from memory.
PC -> MAR MDR -> IR The value in PC is copied to MAR, and the value that MAR points to in memory is copied to MDR automatically. The last step of the fetch cycle is to copy the value in the MDR to the IR.
This ARM privilege level is the user mode, and indicates an unprivileged execute security state where many features of the architecture are unavailable.
PL0
This ARM privilege level is used by all other modes of execute besides user where system software will be executed.
PL1 Processor modes for PL1: FIQ, IRQ, Supervisor, Secure Monitor, Abort, Undefined, System.
This Intel x86 Data Type deals with single instruction multiple data, and performs instructions such as add on more than one piece of data concurrently.
Packed SIMD Typically used for video
This bus protocol sequentially sends groups of bits via multiple data lines.
Parallel Communication The drawback to parallel communication is the overhead required for synchronization. A synchronous bus includes a clock in the control lines and a fixed protocol for communicating that is relative to the clock. The CPU must have some way of checking the status of the deice and waiting until it is ready to transfer.
This typically allows for video cards that require higher transfer rates.
Peripheral Component Interconnect Express (PCI Express)
Image data is comprised of many dots known as what?
Pixels
This bus topology connects two computers together.
Point-to-point Bus
This Intel x86 Data Type allows references to memory locations much like the information found in the MAR in the LMC.
Pointer
This operation gets data from a stack.
Pop To "pop" the information off the stack, access data on top of stack first, then continue popping until you get to BP and the stack is empty. (Not a great explanation for Push and Pop, needs additional description).
This ARM operand addressing mode means that the memory address is the base register value, but an offset is added to or subtracted from the base register value and the result is written back to the base register.
Post-Indexed
This power is used for computer system time and speed.
Power of 10
This ARM operand addressing mode means that the memory address is formed in the same way as for offset addressing, but the memory address is also written back to the base register.
Pre-indexed
This Special Purpose Register (SPR) is used to point the control unit (CU) to the correct memory address of the next instruction.
Program Counter (PC)
This Intel x86 Mode of Operation is the default mode of operations.
Protected Note: An attribute of protected mode in a protected multi-tasking state is commonly referred to as virtual 8086 mode. However, virtual 8086 mode is not a mode and instead a protection attribute of protected mode.
This operation stores data in a stack.
Push First set BP and SP to a memory address (ex: 0xF, arbritary number). Next, store the data in memory address and move SP up one level.
What is a 64 bit grouping called?
Quad word
This ARM Register is the stack pointer.
R13 or SP
This ARM Register is the Link Register, and is used to hold link information.
R14 or LR
This Intel x86 Mode of Operation is used upon power-up and reset of a computer system.
Real-address or Real-MODE
RISC
Reduced Instruction Set computer The RISC architecture computers have one instruction for one operation. The majority of the mobile communications and computing devices run on processors using RISC based architecture.
This Intel x86 Operand Addressing Mode value is located in a register.
Register
This operand value is located in the REG (register), and should be given.
Register
This value can be found in the contents of the REG operand.
Register Indirect REG -> contents
This ARM operand addressing mode (offset) is a value from a general-purpose register.
Register Indirect The value can be added to, or subtracted from, the base register value. Register offsets are useful for accessing arrays or blocks of data.
This Intel x86 calls to privilege levels must be managed to ensure security of a system. This "Ring" is where the OS Kernel is housed.
Ring 0
This "Ring" is where applications are housed.
Ring 3
These "Rings" are where the OS services are housed.
Rings 1 and 2
This Intel x86 Operand Addressing Mode is commonly used implicitly by loading each of the segment registers and allowing the processor to choose the correct register based on the instruction. However, explicit operations are allowed (whatever the hell that means).
Segment
When a program is loaded, it is loaded into four areas called what?
Segments
Bus protocol is the form and means that computer components transmit between the sender and receiver. This protocol sends data sequentially one bit at a time (asynchronous), and relies on handshaking.
Serial Communication
This is attached to the Southbridge and allows for devices such as hard disks and optical devices.
Serial advanced Technology Attachment (SATA)
This is performed when dividing unsigned integers in binary.
Shift Logical Right (SHR) Moves bits in the binary to the right and clears empty bits. shr is used to divide by 2^n, where n is the bits shifted. Pad with ZERO
This Intel x86 General Purpose Registry is the source pointer for string operations.
Source (SI)
This has a PCI express, SATA, USB, and LPC buses.
Southbridge
This Intel x86 General Purpose Registry is the base pointer; points to the base of the stack.
Stack Base Pointer (BP)
This occurs when the caller attempts to use more memory than allocated for a stack.
Stack Overflow
This Intel x86 General Purpose Registry is the stack pointer; points to the top of the stack.
Stack Pointer (SP)
This segment holds temporary data such as data used for calls and returns.
Stack Segment A stack is a data structure that holds temporary data that operates in last in, first out (LIFO) order. When stacks are added to the LMC, two registers are added called the SP and BP, where SP points to the top of the stack and BP points to the bottom of the stack.
This Intel x86 Mode of Operation is the system management mode (SMM) allows for transitions between other modes.
System Management This operation controls the transfer between Real-Mode and Protected Mode.
This segment holds machine code and is more commonly called code segment.
Text/Code Segment
This General Purpose Register (GPR) is used by the arithmetic logic unit (ALU) to execute arithmetic operations and logic decision, as well as temporarily holds input and output data.
The Accumulator (A)
What component of the LMC performs fetch and execute steps by moving data and addresses between the registers and I/O?
The LMC's CPU Control Unit (CU)
True or false? CISC uses a register-to-memory architecture where data processing operations can be performed on both the register and memory?
True
True or false? The ARM calls to privilege levels in much the same way as the x86 calls to privilege rings in order to create a security model.
True
True or false? With regards to Bus Topology, interconnect is a logical connection or link between computer systems, often categorized according to topology.
True
This ARM mode of operation supports software emulation of hardware co-processor.
Undefined (und)
What is a 16 bit grouping called?
Word
What is the integer range of an unsigned byte?
0 to 255
What is the integer range of a double word?
0 to 2^32 minus 1
ASCII, devised by the International Organization for Standardization (ISO) is made up of how many bits, and represents what language?
8 bits (formerly 7 bits with one parity bit) Latin alphabet
What is a system of instructions executed directly by a CPU in binary?
Machine Language
Giga (GB/GHz)
Billion Storage: 2^30 - 1,073,741,824 Speed/Time: 10^9 - 1,000,000,000
This component, also called the processor, is the active part of the computer which contains the data paths and control which adds numbers, tests numbers, and signals I/O devices to activate.
CPU - Central Processing Unit
The stored-program concept is a computer architecture describing an electronic digital computer with what three components?
CPU, Memory, I/O
Name the Op code and mnemonic equivalent for the Data Transfer function "STORE".
Op Code: 3XX Mnemonic: STA
Name the Op code and mnemonic equivalent for the Data Transfer function "LOAD".
Op Code: 5XX Mnemonic: LDA
Name the Op code and mnemonic equivalent for the Control Transfer function "Branch Unconditional".
Op Code: 6XX Mnemonic: BRA
Name the Op code and mnemonic equivalent for the Control Transfer Function "Branch on Zero"
Op Code: 7XX Mnemonic: BRZ
Name the Op code and mnemonic equivalent for the Control Transfer function "Branch on Positive".
Op Code: 8XX Mnemonic: BRP
Name the Op code and mnemonic equivalent for the I/O function "INPUT".
Op Code: 901 Mnemonic: INP
Name the Op code and mnemonic equivalent for the I/O function "OUTPUT".
Op Code: 902 Mnemonic: OUT
The Op Code, comprised of three digits, actually only represents the first digit. The last two digits are called what?
Operand (memory address) The opcode is decoded and represents the operation to be performed. The operand is represented by two digits following the opcode, which is the object manipulated and may be data or the memory address of data.
This is the LMC fetch-decode-execute instruction for INPUT (901/INP).
PC -> MAR MDR -> IR INBOX -> A PC+1 -> PC
This is the LMC fetch-decode-execute instruction for ADD (1XX/ADD).
PC -> MAR MDR -> IR IR [ADDR] -> MAR A + MDR -> A PC+1 -> PC
This is the LMC fetch-decode-execute instruction for SUBTRACT (2XX/SUB).
PC -> MAR MDR -> IR IR [ADDR] -> MAR A - MDR -> A PC+1 -> PC
This is the LMC fetch-decode-execute instruction for STORE (3XX/STA)
PC -> MAR MDR -> IR IR [ADDR] -> MAR A -> MDR PC+1 -> PC
This is the LMC fetch-decode-execute instruction for LOAD (5XX/LDA).
PC -> MAR MDR -> IR IR [ADDR] -> MAR MDR -> A PC+1 -> PC
This is the LMC fetch-decode-execute instruction for Branch Unconditional (6XX/BRA).
PC -> MAR MDR -> IR IR [ADDR] -> PC
When the subroutine is finished, it performs this operation which pops the return address off the stack into the PC.
RET Once the RET operation is completed, the subroutine is finished and the program is back to where it left off. ***Important: RET Procedure*** 1. Pop Stack -> PC 2. SP (down arrow) Stack Pointer moves down.
This is a small amount of storage space within the LMC, and is used to perform operations.
Register
This is performed when multiplying signed integers in binary.
Shift Arithmetic Left (SAL) Moves bits in the binary to the left and clears empty bits, while also preserving the sign bit. Pad with ZERO & preserve SIGN BIT
This is performed when dividing signed integers in binary.
Shift Arithmetic Right (SAR) Moves bits in the binary to the right and replaces empty bits with the same sign as the sign bit. Pad with SIGN BIT & preserve SIGN BIT
This is performed when multiplying unsigned integers in binary.
Shift Logical Left (SHL) Moves bits in the binary to the left and clears each empty bit. SHL is used to multiply by 2^n, where n is the bits shifted. Pad with ZERO
When would lossy compression be used?
When a smaller file is more important than quality. (Lossy results in data deterioration)
When would loseless compression be used?
When data quality is most important. (Loseless retains data quality)
