Computer Organization Exam 2

Correctly fill in values for addressing modes.

(HW problem)

What are the purposes/uses of clocks?

- synchronizes activities of components -Fixed number of clock cycles are required to carry out each data movement or computational operation - Clock frequency, measured in MHz or GHz determines speed of all operations -Clock cycle time is the reciprocal of clock frequency. EX: an 800 MHz clock has a cycle time of 1.25 ns.

What are the diffferent clock parameters?

-Frequency [Hertz] - cycles per second -Period = 1/ Frequency[s] -Duty Cycle [%]= on time/period -Rise Time -Fall Time -Jitter

What are the two ways to interate through an array. (provide code)

.data arr DWORD 1, 2, 3, 4 numEl DWORD 4 .code mov eax, 0 lea ebx, arr mov ecx, numEl 1.{ iterateThru: cmp[ebx], eax ... add ebx, 4 loop iterateThru} 2.{ mov edx, 0 iterateThru: cmp[ebx+(4*edx)], eax ... inc edx loop iterateThru}

Explain microprogrammed control and include diagram

1) Instruction microcode produces control signal changes. 2) Machine instructions are the input for a microprogram that converts the 1s and 0s of an instruction into control signals. 3) Microprogram is stored in firmware, also called the control store. 4) Microcode instruction is retrieved during each clock cycle. 5) These will load into the microinstruction buffer and then go through the decoder, to produce control signals. (see diagram online)

Explain hardwired control and provide a diagram

1) The bit pattern of machine instruction in the IR is decoded by hardware combinational logic. 2) Decoder output works with the control signals of the current system state to produce a new set of control signals. 3) Control signals routed to registers, datapath, and the ALU to execute the specific instruction under execution. (see diagram online)

What are the stages of pipelining?

1. Fetch instruction 2. decode operation 3. calculate effective address of operands 4. fetch operands 5. execute 6. store result.

What 5 things should you consider when designing instruction sets?

1. Instruction length 2. Number of operands 3. Number of addressable registers 4. Memory organization (byte or word) 5. Addressing modes

What are the 6 ways instruction sets are differntiated?

1. Number of bits per instruction 2. Stack-based or register-based 3. Number of explicit operands per instruction 4.Operand location 5.Types of operands 6. Type and size of operands.

What are the 4 ways to store data in CPU?

1. Stack architexture 2. Accumulator 3. General purpose register-memory 4. General purpose register load-store

What are the 4 ways to measure instruction sets?

1. main memory space occupied by program 2. instruction complexity 3. instruction length (in bits) 4. Total number of instructions in the instruction set.

What is the algorithm to convert infix to postfix?

1. read infix expression from left to right one character at a time. 2. Repeat step 3 3. Read symbol a. if symbol is operand put into postfix string b. If symbol is left parenthesis push into stack c. If right parenthesis pop stack off TOP until left parenthesis occur and make postfix expression. d. If operator then 1d. If operator has same or less precedence then operators available at top of stack, then pop all such operators and form postfix string. 2d. push scanned/incoming operator to the stack 4.Until last string encountered 5. Pop all the elements from stack to make staqck empty.

How do you load memory address to the register and iterate arrays? (3 steps)

1. use lea= load effective address, to put the memory address into a register. 2. [register] references the doubleword at the address in the register. 3. increment to the next index of the array until all elements are evaluated.

What is a bus and what does it do?

A bus is a communication pathway connecting two or more devices, or a set of wires that simultaneously convey a single bit alone each line. The CPU shares data with other system components by way of a data bus.

How does associative-mapping cache work? Include diagram

A memory block does not need to go to a specific place like in direct, and it goes anywhere in cache so that it would filll up more efficiently. Memory address is two fields, the Tag and word

What is a macro?

A named sequence of assembly statements that are usually defined at the beginning of program code or be in seperate files. If in a seperate file, it is copied onto program using INCLUDE. The assembler expands the macro during its preprocessing step where it copies the code from the macro directly into the program everywhere the macro is invoked.

What is an interrupt?

A planned but unscheduled event that has a higher priority than routine program execution. Interrupt specific processing (ISR) will be executed in response to an interrupt event. (ISR) = interrupt service routine.

Desribe all RAID levels: 5

Added distributed parity to RAID 4. With distributed parity , some accesses can be serviced concurrently, giving good performance and high reliability. Used in many commercial systems.

Desribe all RAID levels: 0

Also known as drive spanning provides better performance but no error correction. Data is written in blocks across entire array. Has low reliability.

What is bus arbitration and the differences between them?

Arbitration decides what component gets to use and control the bus when. Centralized: Single hardware device controlling bus access called bus controller. This could be a part of the CPU or seperate. Distributed: Each module may claim the bus and control is decided by control logic on all modules.

What are the 3 different fields of cache address?

Block: enough bits to uniquely specify block within cache Offset: enough bits to specific unique location within a block tag:left over bits

What is CPU throughput (CPU time)? How can it be improved?

CPU throughput or time is the time required to run a program. To improve CPU time: -Reduce the number of instructions in a program -Ruduce the number of cycles per instruction -Reduce the number of nanoseconds per clock cycle.

What is the CPU time formula?

CPU time = seconds/program = Instructsion/program X avg. cylces/instruction X seconds/cycle

What are the differences between character and block I/O devices?

Character procces one byte at a time and are typically connected through an interrupt-driven system. Block devices handle bytes in groups, and commonly are storage devices and are efficiently connecting through DMA or channel.

What is the difference between coalesce and compaction?

Coalesce - join large adjacent holes into one large hole Compaction - go through memory and move all holes into one free block (disk defragmentation) (leaves big block at end)

How does set-associative mapping work?

Combines direct and associative mapping. A memory reference maps to a particular location, but it is a set of several cache blocks like associative, not just one block. A memory reference can only map to the subset of cache slots.

Desribe all RAID levels: 2

Contains set of hamming code drives and data drives. The hamming codes provided error detection and correction for the data drives. Performance is poor and cost is high (not used)

What are 2 different types of control units?

Control units keep things synchronized and in order. Signal pattern is same in either type. Hardwired control: implement using digital logic components Microprogrammed control: a small program is placed into read-only memory (ROM)

Draw a diagram explaining direct memory access

DMA and CPU share the bus, but DMA has a higher priority and steals memory cycles from CPU. (refer to slides)

What is the difference between SRAM and DRAM?

DRAM - consists of capacitors, dynamic memory, cheaper and simpler, slowly leaks overtime so it must be refreshed to prevent data loss, denser, has larger memory units SRAM: static, much faster memory, used for cache, made of D-flip-flops

What is the difference between dedicated and multiplexed buses? Pros and cons?

Dedicated buses use seperate data & address lines. Multiplexed buses have shared lines meaning a time share. Have a address valid or data valid control line. While the multiplexed has few lines it has more complex control and it slows ultimate performance.

How does memory-mapped I/O work?

Devices share same address space with main memory so each I/O device has own block. Looks just like a memory access from CPU point of view and so it uses the same instructions to move data to and from and it simplifies everything.

Describe interrupt-driven I/O with diagram

Each device connects its interrupt line to the interrupt controller. The controller alerts for any interrupts. (check slides)

Show the 6-stage pipeline in UMl form

FI(fetch instruction) => DI(decode instruction) =>CO(calculate operands) =>(unconditional branch?) if yes (jmp update PC), if no FO(Fetch operands) => EI(execute instruction) =>WO (write operands) => (branch or interrupted?) Yes => update PC => empty pipe => (reiterate) FI, if no FI.

What are the defs of hit, miss, hit rate, miss rate, hit-time, & miss-penalty?

Hit: when data is found at a given memory level. Miss: when it is not found Hit-rate: is the percentage of time data is found at a given memory level Miss rate: percentage of time data is not (1-hit rate) hit time: time required to access data at a given memory level miss penalty: time required to process a miss, including time it takes to replace a block of memory plus the time it takes to deliver the data to the processor.

What are 5 different addressing modes?

Immediate addressing: data is part of instruction Direct addressing: the address of the data is given in instruction Register addressing: the data is located in a register Indirect addressing: gives the address of the address of the data in the instruction register indirect addressing: uses a register to store the address of the data.

Show two diagrams comparing low and high order interleaving. Give another showing the bits and explain.

In high order, the high order 4 bits select the chip/bank. In low order the low-order 4 bits select the bank/chip. (look up diagrams)

What is the interrupt process? Draw diagram.

In the instruction cycle, after we fetch the instruction we will execute it. It will then check if there is an interrupt and if there is it will process it. It will then recontinue the cycle and fetch the next instruction. If program will halt while processing an interrupt.

What are all the addrssing modes w/diagrams? (last 5 +2 more)

Indexed addressing: uses a register as an offset which is added to the address in the operand to determine the effective address of the data. Based addressing: similar except that a base register is used instead of an index register.

How does LRU algorithms work for replacement?

It keeps track of the last time a block was accessed and evicts the block that has been sitting unused the longest. It makes it slower and more complex due to keeping a history for each block.

(40) Show the 2-address way to evalate infix expression Z= X*Y +W *U

Load R1, X Mult R1, Y Load R2, W Mult R2, U Add R1, R2 Store Z, R1

(40) Show the 1 address way to evalate infix expression Z= X*Y +W *U

Load X Mult Y Store Temp Load W Mult U Add Temp Store Z

Waht is loading and what happens?

Loading a circuit is when a component or load is connected to the circuit and affecting the circuits original properties. This cn cause faulty logic levels in downstream systems and lead to logic errors and could result in catastrophic failure in controlled system.

What are the two types of shifts? Show example

Logical - shl, shr arithmetic - sal, sar

Describe all shift instructions and show examples

Logical shift Left(shl) & Arithetic shift left(sal): lowest bit filled with 0, highest copied to CF, bit in CF before is discarded. Logical shift right (shr): highest bit filled with 0, lowest bit to CF, CF bit discarded. Arithmetic shift right(sar): copies of original sign bit fill highest bit, lowest bit copied to CF.

What are the 3 different schedulers?

Long term scheduler - used to control multi programming( how many processes line up to use the processor) Medium term scheduler = use to control use of memory (and virtual memory) Short term - which process gets to use the processer.

Difference between high and low-order interleaving?

Low-order: the low order bits of the address specify which memory bank contains the address of interest. High-Order: the high order address bits specify the memory bank.

What is the difference between macros & procedures?

Macros expand the code into program each time they are invoked whereas procedures do not expand. Macros can be executed quicker due to lack of overhead of passing parameters but there are usually more bytes of object code with a macro especially with repetitive use.

Draw the pyramid of memory organization hierarchy

Made of registers, cache, main memory, and virtual memory and storage devices

What are the two types of buses commonly found in computer systems? Draw their diagrams

Multipoint and point to point

Explain the NOT instruction and what it does.

No flags affected Performs one's complement (reverses bits)

Describe the paging process (dif between page and pageframing)

Page Frames: split memory into equal sized, small chunks Pages: split programs/processes into equal sized small chunks paging allocates required number of page frames to a process, the operating system maintains list of free frames, and does not require contiguous page frames.

What is page fault and demand paging?

Page fault: required page is not in memory so the OS must swap in required page, and may need to swap out a page to make space Demand paging: does not require all pages of a process in memory and brings in pages as required.

What is swapping and when is it a solution? Include diagram

Problem: I/o is so slow that even in multi-programming system CPU is idle all the time Solutions: Swapping Swapping is swapping processes in and out as space in memory is cleared by the completion of processes. If no process is ready, it will swap out a blocked process to intermediate queue, swap in a ready process or a new one.

Find the best upgrade using Amdahls law: - We can upgrade CPU to make it 50% faster for 10k or upgrade disk drives for 7k to make them 150% faster. Processes spend 70% of time running in CPU and 30% waiting on disk service. What upgrade would better?

Processor option: f = .70, k = 1.5 so S = 1/ (.3 +(0.7/.5) offers a 30% speedup for $333. Disk drive: f = .3, k = 2.5 so S = 1/ (.7 + 0.3/2.5) = 22% speedup for 318. Disk drive should be updated for best cost.

What are the 5 different ways I/O can be controlled?

Programmed: reserves a register for each I/O device. each register is continually polled to detect data arrival. Interrupt-Driven: allows CPU to do other things until I/O is requested. Memory-mapped: shares memory address space between I/O devices and program memory. Direct memory access (DMA): offloads I/O processing to a special purpose chip that takes care of the details. Channel: uses dedicated I/O processors.

What is cache, its purpose, and its attributes?

Purpose: speed up accesses, stores data closer to CPU, to get have recently and frequently used data read to go so searches take less time Attributes: smaller than main memory, access time is much faster, accessed by content. A single large cache memory isnt always desirable.

(40) Show the stack way to evalate infix expression Z= X*Y +W *U

Push X Push Y mult Push W Push U mult Add Push Z

What is the difference between ROM & RAM?

ROM: non-volatile, read only, byte addressable, used for microprogramming, librarys, flash with bulk addressable memory. RAM: volatile, two types (DRAM &SRAM)

What are the reasons that a pipeline may be flushed?

Resource conflicts, data dependencies, and conditional branching

What are the properties of harddrive disks that determine speed?

Seek time - time it takes for an arm to move into postition over desired cyclinder rotational delay - time it takes for desired sector to move into position beneath read/write head Seek time + rotational delay = access time

What are the two types of magnetic tape? + diagrams

Serperntine: used in digital linear tape and quarter inch cartridge systems twist back and forth like snake. Helical scan: Digital audio tape systems, and are diagonal like a wrapped around rope.

Desribe all RAID levels: 4

Similar to adding parity disks to RAID 0. Data is written in blocks across the data disks, and a parity block is written to the redundant drive. Would be feasible if all record blocks were the same size.

What is rotation and what are the differences between the two shifts?

Similar to shift, bits are shifted off of one end but are rotated to the opposite end. ROR: bit rotated off 0 copied to CF and rotated to 7. ROL: bit rotated off the left copied to right end (0) and copied to CF.

How does direct-mapping cache work?

Simplest cache mapping. Y = X mod N block location in cache = the block of memory X / N blocks Maps in groups. 7, 17, 27 Fixed locaton for a given block.

Whats the equation for theoretical speedup?

Speedup S = nTn/(k+n-1)Tp or without pipeline/with pipeline Theoretical speedup = limit of that equation = kTp/Tp = k.

What is partitioning?

Splitting memory into sections to allow allocations of processes. Fixed-size may not be big enough and wastes memory. Variable allocates exact size to convserve space but this leads to holes being made at end of memory. Use fragmentation

Draw the diagram for the 4 ways to store data in CPU.

Stack: Push A, Push B, Add, Pop C Accumulator: load A, add B, store C. Register-memory: load R1, A - Add R1, B - Store C, R1 Register (load-store) : (load R1, A -- Load R2, B -- Add R3, R1, R2 --Store C, R3 Add diagrams

Desribe all RAID levels: 3

Stripes bits across a set of data ddrives and provides a seperate disk for parity. (parity is the XOR of the data bits) Not suitable for commerical applications, but good for personal systems. (slow writes, high transfer rates)

What is switch debouncing?

Switches are mechanical devices, and when they are flipped it makes/breaks contacts multiple times, this is called bouncing. The processor is fast enough to see each bounce as individual input, and to stop this we debounce it with HW/SW techniques. HW: switch debounce interface circuit. SW: software delays upon switch activation long enough to outlast switch bouncing.

map the time, signal and meanings together

T0 = assert write = bus is needed for writing (not reading) t1 = assert address = indicates where bytes will be written t2 = assert request = request write to address on address lines t3 = assert ready = acknowledges request, bytes placed on data lines. t4-t7 = data lines = write data (takes some cycles) t8 = lower ready = releases bus.

What is the difference between Unified & Harvard cache? Include diagram

The cache we discussed is unified, where both instructions and data are cached. Harvard cache is used by systems that seperate caches for data and instructions. The seperation of data from instructions provides better locality at the cost of greater complexity. Unified = CPU <-> CACHE<->Main memory harvard = CPU <->Data cache<-> main memory <->instruction cache ->CPU

What is the equation and meaning of Amdahl's Law?

The overall performance of a system is a result of its parts interacting so the system is most improved when the performance of the most heavily used components is improved. S = 1/ (1-f) +(f/k) S = overall speedup F = fraction of work performed by a faster component k = speedup of the faster component.

How are multiple interrupts processed? Include diagram

The processer will disbale interrupts and ignore further interrupts while processing one interrupt. Those interrupts remain pending and are checked after 1st interrupt has been processed. They are handled in sequence as they occur. If they occur all at once, the low priority interrupts can be interrupted by higher priority interrupts and when those have been processed the the processor returns to previous interrupt.

What is the equation to find the time to complete n-tasks?

Theoretical speedup is modeled by the equation. tp is the Time per satge and each instruction represents a task T, in the pipeline. The 1st task takes (k x Tp) time to complete. The remaining (n-1) tasks emerge from the pipeline one per cycle. So the time it takes to complete the remaining tasks is (n-1)Tp. time to complete n-tasks: = (k x Tp) + (n-1)Tp = (k+n-1)Tp

Allocate and identify contents in table

This one

Draw the diagram for swapping

This one and up above

What is thrashing and its solutions?

Thrashing is when there are too many processes in too little memory and swapping is constantly going on and its all the OS is doing. No real work gets done and the disk light is on all the time. Solutions: Good page replacement algorithms, reduce number of processes running, and fit more memory.

Draw the diagram for classification of computery memory

Types -> Ram (SRAM & Dram) vs ROM (PROM, EPROM, EEPROM)

Explain the OR instruction and what it does.

Use to set(1) selected bits without affecting others. Put 1 in bit you want to change and operate. Flags affected: -CF, OF are both cleared -SF, ZF set or unset based on result -PF set or unset based on parity of least significant byte of result.

Explain the AND instruction and what it does.

Used to clear or 0 selected bits without changing others. Put 0 in bits you want to change, -> and AL, change code. Flags affected: -CF, OF are both cleared -SF, ZF set or unset based on result -PF set or unset based on parity of least significant byte of result.

Explain the XOR instruction and what it does.

Uses: reversable property allows simple data encryption. Can also use to toggle bit 5 of an 8-bit to convert cases in letters. Bit retains current state if xor'd with 0. Toggles if xor'd with 1. Put 1 at the bit you want to toggle. Flags affected: -CF, OF are both cleared -SF, ZF set or unset based on result -PF set or unset based on parity of least significant byte of result.

What are the 8 different voltage and current characteristics?

V(oh): lowest guaranteed output voltage for logic high. V(ol): highest guaranteed output voltage for logic low. I(oh): the output for logic high (- current source) I(ol): the output for logic low (+ current sink). V(ih): lowest input voltage guaranteed as logic high V(il): highest input voltage guaranteed for logic low. I(ih): the input current for logic high (+ current sink) I(oh): the input current for logic low (- source sink).

What are the different varieties for DVDS and the difference between DVDS and CD-ROMs?

Varieties: Single-sided, single layer to double-sided, double layer (and in between) The DVD can hold more than 17GB where CD-ROM holds 650mb. DVD has a different laser using a shorter wavelength.

How can you use xor to zero a register?

When xor'd with self, it will zero out all bits. Write table.

What is tri-state logic?

Where logic tables can be made wih 3 values, high, low and high-Z High-Z means that the output inable is off, so it cannot give a value. It is ignored. If output-enable is L, it results in High-Z. Think of and table.

What is write policy and when is it used?

Write policy is used to determine how to write dirty blocks back to memory. This is either write back, or write through.

What is the difference between write back and write through?

Write through: all writes go to main memory and cache, it updates both sumultaneously on every write. Multiple CPUs can moniter main memory to keep local cache up to date, causes a lot of traffic and it slows down writes. Processor ->Cache memory and source memory Write back (copyback): updates memory only when block is selected for replacement, memory traffic is minimized, but the memory doesn't always agree with the value in cache causing problems. Processor -> cache memory ->source memory

Convert an infix to a postfix expression and show all steps. Z= (X*Y) +(W*U)

Z= (X*Y) +(W*U) becomes Z = XY *WU*+

Desribe all RAID levels: 1

also known as disk mirroring provides 100% redundancy and good performance. Two matched sets of disks containing same data Disadvantage = cost of two hard drives

what are I/O buses?

i/o buses operate asynchronously and requests for access must be arbirtrated among devices, control lines activate devices, raise signals and reset devices. The number of data lines is the width of the bus and the clock coordinates activities.

What is RAID's purpose, and which ones are used most?

invented to address problems of disk reliability, cost, and performance. Data is stored across many disks with extra ones so that it has error correction or redundancy. RAID 6 , DP and 10 are most used today.

(40) Show the 3-address way to evalate infix expression Z= X*Y +W *U

mult R1, X, Y mult R2, W, U add Z, R2, R1

Show the diagram of a general instruction format

opcode(1 or 2 bytes) ->Mod-R/M(0,1 bytes)[Mod, reg/opcode, R/M] ->SIB(0 or 1)[SS, Index, Base] -> Displacement (0,1,2, or 4) -> immediate (0,1,2 or 4)

What is the difference between parallel and serial data transmissions? Inlcude diagram

parallel data transmission sends their encoding signals simultaneously, while serial does it one bit at a time. Parallel requires a conductor for each bit along seperate lines meaning much fatter cabes. Serial communications: require fewer conductors, are less susceptible to damage, are less expensive and can transmit farther.

Draw the different diagrams of cache vs memory

see slides

Use a stack to evaluate postfix expressions w/ assemblty code. 2 3 + 6 3/-

stack: 3 2 post: +63/- pop 2 and 3 and operate with +, push back on stack stack: 5 postfix:63/- stack 365 postfix /- pop 2 and 6, operate, push back on stack stack: 35 postfix - pop from stack, operate and push back on 5-3 = 2 result = 2

What is the principle of locality?

tells us that once a byte is accessed, it is likely that a nearby data element will be needed soon. (tend to reuse data)

What are the 3 forms of locality?

temporal: recently-addressed data elements tend to be accessed again spatial: accesses tend to cluster Sequential: instructions tend to be accessed sequentially.

Describe transfer rate, average latency, and mean time to failure.

transfer rate: gives us the rate at which data can be read from the disk Average latency: function of rotational speed = 30 seconds/ disk rotate speed * 500ms/half second Mean time to failure: statistically determined value that isnt truly accurate that measures the disk life.