ECE 252 Exam Two
execute operation
do the operation using the source operands (processing unit) - ADD: signal ALU to do ADD - LDR: does nothing, work has already been done in copying the data from memory, ALU is not used.
what is an element in memory? an element's value?
element - storage loc in the mem array value - the data (bit pattern) stored in the element
what is the function of a clock circuit
ensures that all FSM transitions are done synchronously transitions happen at the start of each clock cycle faster clock = faster transitions
determine output of RS Latch given current state
first of all, output is different depending on given state, but it generally functions by one of the two inputs being dropped down to zero, then brought back up to one. If S drops to zero and is brought back up, the output is "set" to one. If R is, the output is "reset" to 0. If input is 00, the circuit will not function, and if input is 11, the circuit will determine next state based on prev inputs (?) MAKE SURE TO TRACE IT
FSM vs. Universal Computing Device
fsm normally is programmed to do a specific task (danger sign) UCS is able to load and run programs, is far more complicated
fetch instructions
gets next instruction from mem, puts into IR in control unit 1. copy contents of PC into MAR (one machine cycle) 2. send read signal to memory (could take multiple cycles) 3. read contents of MDR into IR (copy data from memory location) 4. increment PC, pointing it to the next instruction
fetch operands
gets the source operands for the operation ADD: copy data from registers to ALU for operations LDR: copy data from memory into a register
in a gated D-latch, what must the WE be set to for D's value to pass through? What happens if D = 1? = 0?
if d=1, s = 0 and r = 1, sets to 1 if d=0, s=1, r=0, resets to 0 Note that you can simply trace this, and most importantly, the RS Latch is simply set to whatever D's value is when the WE is turned on.
what part of the state machine takes in inputs? which part takes in the clock signal? where does output come out from?
inputs go to combinational logic (computes next state and next output), clock goes to sequential, outputs come from combo
what is a full adder designed to do?
it computes the binary sum of all possible combinations of bits A and B with a given carry in bit C. It takes in those three inputs, and outputs the sum and the carryout bit.
what does a finite state machine do?
it computes the next state and the output based on the current state and input
what does "moving the control unit to the next state" mean?
it either moves on to the next instruction, or goes to the next step of the current instruction. some instructions take several cycles.
what is the function of a multiplexer(Mux)
it picks one of the inputs to pass through the multiplexer based on a selector input (s).
how many selector bits does a mux need based on the number of inputs
it takes in 2^n inputs and requires n selector bits
how is a decoder implemented?
it takes in n inputs, and for each combination of these n inputs (ie A=1, B=0, C=0) there is an AND gate. All of the AND gates are capable of outputting 1, but only one can at a time, because they each have a specific combination of inputs that will result in 1 as the output. for example, a two bit decoder is a circuit with 4 AND gates, and the gate that will result in 1 given the input A=1,B=0 will take the input from A and invert the input from B, so that the output of the AND gate will be 1.
LDR operation: structure of instruction, description of process
load operation opcode: 0110 Structure= 0110 DST Base Offset where DST is the register where the contents will be stored, the contents being the data stored at the memory location whose address is equal to the contents of the Base register, added in binary to the offset.
addressability
memory location's size in bits. standard is 8 bits, called "byte addressability"
n-type vs p-type
n closes with 2.4-2.9 V, connects to ground resulting in 0 output V p closes with 0-0.5 V, connects to power resulting in 1 output V (has the little circle indicating it accepts 0 as input) both gates give output opposite of input
two parts of instructions
opcode - operation to perform operands - data/locations to be used in operation
ADD operation: structure of instruction, description of process
opcode: 0001 Structure= 0001 DST SRC1 000 SRC2 where DST is the register # where the sum will be stored, and SRC1 and 2 are the two registers whos contents need to be summed
truth table for NOR
opposite of OR
store result
puts the result into a destination register or into memory - ADD: result stored in destination register - STR: result stored in memory at the address computed in the "evaluate address" step
RAM, SRAM, DRAM
random access memory can access memory locations in any order. there are two types of RAM: SRAM - static, faster but smaller capacity, maintains data when power is off DRAM - dynamic, slower but much larger capacity, doesn't have good long term storage, and bit storage must be periodically refreshed
How does a machine exert control over the flow of execution?
requires an instruction (JMP in LC-3) thats able to load a new address into the PC - jump: unconditional, always changes the PC - branch: conditional instruction, only changes the PC under certain condition
parallel vs serial connections
serial (in a straight line) requires both outputs correct to close their gates, whereas a parallel (each gate has its own way of connecting either to the ground or power) requires at least one of the inputs to be correct, resulting in at least one of the gates closing.
what is a "tick," what does it cause to happen
signifies the start of a computer cycle, typically occuring on the rising edge of the clock cycle. It keeps the control center running, and will move the computer to the next state
Where are registers located? what are the characteristics of a register?
small, fast, temporary storage (frequent changes to contents).
RS Latch purpose
stores 1 bit of data (can be set to 0 or set to 1)
where is an instruction interpreted? How is it encoded?
the control unit orchestrates its FULL execution (all of it or none of it), encoded as a sequence of bits (opcode + operands)
what causes state transitions in a FSM
the inputs
what is logical completeness, what does it apply to
the set of gates {AND, OR, NOT} is logically complete because any truth table can be implemented using some combination of these gates.
draw a full adder.
there does not need to be an AND gate for each possible combination, only for those which correspond to sums that either are 1 or have a carryout bit. There is an OR gate for the carryout bit and an OR gate for the sum bit. the AND gates for combinations that result in a sum of 1 will connect to the OR gate producing the sum, and the AND gates for combos that have a carryout connect to the OR gate that outputs the carryout bit.
where are the ALU and the FLU located? what is their purpose
they are both in the processing unit, arithmetic/logic unit which does integer math and logic operations, floating point unit which does floating point math. They each connect to registers which store the results of their computations, as well as provide them data for computations.
what is a hertz
unit of frequency, = number of cycles per second
word
unit of info transmitted in a processor, typically 64 bits/8 bytes in a computer
draw out the 4 input mux
we assume that if the selector bits are accepted by the AND gate, the data will also be accepted by the AND gate
how are gates with more than two inputs implemented?
with a circuit of multiple gates that only accept two inputs, EX: A and B and C -> do one gate for A and B, whose result is and-ed with C to get the final output
How do you easily convert between and AND gate and an OR gate?
you invert (NOT) both the inputs and outputs (Demorgan's Law)
Combinational Logic, examples
"decision element" stores no memory, and its output is based solely on the inputs it has in a given moment. given the same input, a combinational circuit will always produce the same results this can involve AND OR NOT
Components of the Von Neumann Model:
(a) Memory: Storage of information (data/program) (b) Processing Unit: Computation/Processing of Information (c) Input: Means of getting information into the computer. e.g. keyboard, mouse (d) Output: Means of getting information out of the computer. e.g. printer, monitor (e) Control Unit: Makes sure that all the other parts perform their tasks correctly and at the correct time.
what parts of a FSM are specified by combinational logic? sequential logic?
- its finite number of states are stored by the sequential logic - specification of all forms of state transitions are in combinational logic (takes stored state info and changes it, moves it back into the sequential logic/storage) - specification of what causes each possible output in combinational logic
what are the valid ranges of voltages which represent 0 and 1? what is the invalid zone?
0-0.5 and 2.4-2.9, between these is invalid
order of the instruction execution cycle
1. fetch instructions (FI) 2. decode instructions (DI) 3. evaluate address (EA) 4. fetch operands (FO) 5. execute operation (Ex) 6. store result (SR)
what does the control unit do?
1. reads current instruction from the memory location with the address stored in the PC 2. interprets the current instruction stored in the IR and signals other components how to execute it
steps to implementing circuits for a simple finite state machine given a state diagram
1. truth table! given each possible input, what will the next state (S1 S0) be given each possible current state (S1 S0) 2. identify from the truth table which current states in combination with a specific input will result in S1 needing an input of 1, same with S0 3. make an and gate for each unique current state identified above, in a column. label each as (input bit, S1, S0) and flip sideways, write those three bits along the left side of the gate so you have your 'not' circles in the right place 4. create input line, connect it to the bottom input of each and gate. 5. draw storage bins for s1 and s0, connect both to clock 6. connect middle input on and gates to s1 storage, top inputs to s0 storage 7. create an OR gate for s1 and s2, as well as for any relevant outputs. Label with states that cause them to be set to 1, make the relevant connections between the AND/OR gates 8. connect each OR gate to its storage location
How long is an LC-3 instruction?
16 bits (first 4 are opcode)
word size in the LC-3
16 bits.
How many registers does the LC-3 have?
8! R0 - R7
how is a multiplexer(Mux) implemented?
a series of AND gates, each connected to one specific input as well as the selector. They are set up so that one of the AND gates will output 1, based on the selector input. For a two input mux, the selector only needs to be 1 bit (one AND will pass if S=0, the other if S=1). a four input mux needs the selector to be two bits, one combination for each of the four inputs (00 11 10 01). these are all then connected to an OR gate. All but one of the results will be 0, so the non-zero result selected will pass through the OR gate.
what is the text representation of the output of A after going through a NOT gate?
A with a line over it
which gate corresponds to this rule? if all inputs are 1 the output is 1 ->
AND
what is the text rep of the output of A and B going thru an AND gate? NAND gate?
AND -> AB or A(dot)B NAND -> Above but with a line over it
decode instruction
After an instruction is brought to the CPU, the control unit breaks down that instruction and gives the necessary data to the ALU/FPU 1. identify the opcode (determines structure of the operands) 2. identify the operands (if any) from the remaining bits 3. decoder outputs signal to processing unit to say which operation to do
register structure
a single register a series of gated D latches (corresponding to each bit of data) each with their own data input lines, and the same WE connection.
what is the state of a system?
a snapshot of all the relevant elements of that system at a moment in time
instruction register
a special memory location in the control center that stores the current instruction that is being executed
Three parts of a simple computer
Control unit - interprets/executes instructions (sequential and combinational logic FSM) Processing unit - performs operations Memory - stores data and instructions (program)
what does JMP do in the LC-3? How is it structured?
During the execute phase, the PC is wiped of the address it was incremented to during the FETCH phase. During the EXECUTE phase, the PC is loaded with the address contained in the register # specified in the operands section of the instruction. The next FETCH cycle will use this address to fetch its instructions, and the PC will increment from here. 1100-000-(three digit binary indicating which reg is copied)-000000
what is a decoder designed to do?
It takes n inputs and has 2^n outputs from AND gates corresponding to each possible combination of inputs. for any given input combination, one of the AND gates will output 1, while the others output 0. We design it so that the AND gate which outputs 1 when the input is, for example, 111, connects to some next circuit whose needed input is 111.
two functions of memory
LOAD- read a value from memory location at specified address. 1. write the address into the MAR 2. send a "read" signal to memory 3. copy the data into the MDR STORE - writes a value to a specified memory location 1. write/copy the data into MDR 2. write address into MAR 3. send a "write" signal to memory
evaluate address
computes address for instructions that access memory (LDR requires you to add the remaining bits to the address stored in the specified register, that computation would be done here)
two physical parts of memory
MAR: memory address register capable of storing a single memory address MDR: memory data register capable of storing data from a single mem location
which gate corresponds to this rule? if all inputs are 1 the output is 0 ->
NAND
which gate corresponds to this rule? if any inputs are 1 the output is 0 ->
NOR
which gate corresponds to this rule? if any inputs are 1 the output is 1 ->
OR
what is the text rep of the output of A and B going thru an OR gate? NOR gate?
OR -> A+B NOR -> A+B with a line over it
Gated D Latch
R-S latch storing one bit of data that has a gate which determines whether the data stored in the R-S latch can be set/reset. Data d goes into the RS Latch only if the WE (write enable) is set to one. this data will change one of the inputs to the RS latch, thus changing the data
what is the general structure of computer memory
conceptually similar to a 1-D array of storage bins, each of the same size (capable of holding the same max number of bits)
Program Counter (PC)
contains the address of the next instruction to be executed in the control center
How does a program control the flow of execution?
a program executes line by line, top to bottom. This can be further controlled/changed through method calls, conditional statements, loops, recursion, anything that switches up that top to bottom, step by step order
address space, size/range of AS?
Total amount of memory addresses that an address bus can contain, number of uniquely usable mem locations usually in the range 0 -> 2^(n-1) where n is the number of bits used to specify an address
Data/Address Bus
Transfers data and addresses between processing unit, and memory, introduced as a part of the processing unit. It is the "word size" of the computer typically, so the size of info that is being passed around. (LC-3 = 16 bits)
what is a driver?
controls access to an input/output device (ie keyboard, discs, speaker)
draw an abstract circuit which adds two 4-bit binary numbers A + B, written (A3)(A2)(A1)(A0) + (B3)(B2)(B1)(B0)
a series of 4 full adders. the first adder takes in c=0, a0 and b0. the next adder takes in c= carryout from the first adder, and b1 + a1. of sum S, the first adder will output S0, the second S1, so on until we have all four bits and the final carryout from the 4th adder.
how is combinational logic used to implement different actions in the LC-3 based on the opcode?
a decoder is used, and each individual AND gate is connected to the shit that needs to be implemented given that individual opcode/input combo
byte
a group of 8 bits
