Embedded Systems CHP 1 & 2

What rate can define the timing in the SPI? A) Bit rate B) Clock speed C) Speed Rate D) Voltage Rate

B) Clock speed. The slave doesn't have to know the communication rate, but it knows the max and min usually. The Master is responsible for setting up communication speed - the output from the master has a speed and that is the clock speed. In SCI, the answer is bit rate. in SCI, when we tx 1 byte, its 8,7,6,5 etc data bits (usually 8), 1 start, 1 stop; normally 10 bits total. SPI can do 8 or 16 bits in 1 tx. So clock speed and bit rate aren't 1:1.

Which of the following uses clock edge to generate an interrupt? A) Edge Triggered B) Level-triggered C) Software interrupt D) None of the mentioned

A) Edge triggered. >2.7V is high and <2.4V is low, but we store 0 or non-0 values in the registers.

Which of the following performs the START signal in I2C? A) Master B) Slave C) CPU D) Memory

A) Master The master initiates communication. The START signal is performed by the master by making the SCL and SDA pin high.

Which of the following offers CPUs with integrated memory or peripheral interfaces. A) Microcontroller B) Microprocessor C) Embedded System D) Memory System

A) Microcontroller. A microcontroller has memory and other peripherals integrated into one chip. A microprocessor only has an ALU, all memory and peripheral devices are separate.

Which pin provides the mechanism for transfer of data in I2C? A) SDA B) SCL C) SPDR D) Interrupt pin

A) SDA, the serial data line

Which of the following are the three hardware signals in I2C? A) START, STOP, ACKNOWLEDGE B) STOP, TERMINATE, END C) START, SCL, SDA D) STOP, SCL, SDA

A) START, STOP, ACKNOWLEDGE

Which are the two lines used in SPI or SSI? A) MISO and MOSI B) MOSI and CLK C) CLK and CS D) All of the above

D) All of the above

In UART, which of the signals is set to one if no data is transmitted? A) READY B) START C) STOP D) TXD

D) TXD

What does the RISC processor such as the ARM Cortex use to hold the data? a) flag register b) accumulator c) internal data register d) stack register

c) internal data register / general SFR (special fxn register) (the 12 of them)

Which of the scheduling algorithm are based on the assumption that tasks are executed until they are done? a) periodic task b) aperiodic task c) non-preemptive scheduling d) preemptive scheduling

c) non-preemptive scheduling (co-operative). Doesn't matter if it's periodic or aperiodic. And it's not preemptive bc control can't be taken by another task.

Which of them is a memory that is allocated to the program in FIFO pattern? a) stack b) index c) queue d) base

c) queue. Stack is LIFO. Index is used to index into the information.

What is an "Entry point" in an application? a) A place where execution can start b) The location of the main () function c) The lowest address contained in a program image d) A location where the linker can store additional information

a) A place where execution can start. Eg if we service an interrupt, we can come back to the entry point instead of starting all over.

Which of the following are interfaced as outputs to the parallel ports? a) LEDs b) switch c) alphanumeric display d) seven segmented display

a) LEDs c) alphanumeric display d) seven segmented display Anything controlled by the micro (on the output side) Switch is normally an input

Data can flow only in one direction all of the times in a _________ mode. a) simplex b) half-duplex c) full-duplex d) None of the choices are correct

a) Simplex

A Last-In-First-Out data storage system on the computer used to remember data temporarily is known as Stack a) TRUE b) FALSE

a) TRUE

A physical connection between the computer and its outside world is the Port a) TRUE b) FALSE

a) TRUE

A positive logic is a type of logic where the voltage representing FALSE is less than the voltage representing TRUE. a) TRUE b) FALSE

a) TRUE

In ADC, the quantization error depends on the number of bits which is used to represent the analog value. a) TRUE b) FALSE

a) TRUE

In ARM architecture, Registers can contain an address, and the instruction reads or writes a) TRUE b) FALSE

a) TRUE

In ARM4 Cortex Architecture, Interrupts are not disabled to allow an interrupt with a higher priority (lower value in priority register) to interrupt a) TRUE b) FALSE

a) TRUE

START and STOP are the handshake signals in UART a) TRUE b) FALSE

a) TRUE

Soft real-time — systems where deadlines are important but which will still function correctly if deadlines are occasionally missed a) TRUE b) FALSE

a) TRUE

To decouple (separate) the execution of the ISR with the main program, a FIFO queue is necessary. a) TRUE b) FALSE

a) TRUE, but it is also priority based. If all have same priority, FIFO is main rule.

CS (Chip Select) performs the slave selection SPI(or SSI) a) TRUE b) FALSE

a) TRUE. This is how we select the device we wanna talk to. I2C broadcasts to all connected.

Reset vector (value to which the PC is initialized on power up) a) TRUE b) FALSE

a) TRUE. When we first start, whatever is in program counter will execute, then PC changes to execute other commands.

A Task is in an Embedded system architecture is a C function call or Assembly routine that is executed in a proper context a) TRUE b) FALSE

a) TRUE. task is executed as a job and the job is a c fxn. Our tasks in RTOS are in C, but they could also be assembly.

Which of the following defines the task which event-driven, i.e it does not execute at very defined unit of time? a) aperiodic task b) periodic task c) job d) none of the mentioned

a) aperiodic task

Which of these is an area for temporary memory storage? a) buffer b) register c) table d) flag

a) buffer eg array or linked list

Built-in set of machine code instructions of computer are called a) instruction set b) transfer of data c) logical operations d) logical set

a) instruction set

Which interrupts are generated by the on-chip peripherals? a) internal b) external c) software d) hardware

a) internal. eg. Tx completed internal interrupt. External interrupts can be set on the Rx side.

How is memory accessed in RISC architecture such as the ARM (Advanced RISC Machine) Cortex? a) load and store instruction b) opcode instruction c) memory instruction d) bus instruction

a) load and store instruction

How is memory accessed in RISC architecture such as the TIVA C ARM Cortex? a) load and store instruction b) opcode instruction c) memory instruction d) bus instruction

a) load and store instruction

Which of the following is approximated during hardware/software partitioning, during task-level concurrency management? a) scheduling b) compilation c) task-level concurrency management d) high-level transformation

a) scheduling. During design time, we talk about approximation of scheduling bc we have to estimate when the tasks will be done executing.

Which of the following cannot transfer multiple bits of data simultaneously? a) serial port b) sequential port c) concurrent unit d) parallel port

a) serial port

Which of the following is the pin efficient method of communicating between other devices? a) serial port b) parallel port c) peripheral port d) memory port

a) serial port. Parallel is not efficient because we need 8 lines or 16 lines, which may not be available in microprocessor. For peripheral ports, we also need a timer and interrupts - which is what UART/SCI is (the 3 pieces together). Peripheral by itself may not include the other 2 necessary components.

Which signal is used to select the slave in the SSI peripheral interfacing? a) slave select b) master select c) clock signal d) none of the above

a) slave select. I2C modules all rx same signal from 2 lines only.

Which of the following helps in the generation of waveforms? a) timer b) inputs c) outputs d) memory

a) timer - used to control output, read inputs. But you cannot use output or input to create waveform.

Which of the following is the common method for connecting the peripheral to the processor? a) internal interrupts b) external interrupts c) software d) exception

b) external interrupts.

Data can flow only in one of both directions all of the times in a _________ mode. a) simplex b) half-duplex c) full-duplex d) None of the mentioned

b) half-duplex

The execution of the task is known as a) memory map b) job c) loop d) ISR

b) job - which can be implemented by a fxn.

Where is memory address stored in a C program? a) stack b) pointer c) register d) accumulator

b) pointer. C used to be called the language of pointers bc it allows you to access memory directly using pointers. Accumulator is same as register.

Which of the following can own and control the resources? A) Stack B) Task C) System D) Peripheral

B) Task

_______ is the process of converting digital data to a digital signal. a) Sampling b) Line coding c) Synchronization d) none of the mentioned

b) Line coding - data signal sent in digital form. 4 ways: digital-digital, digital-analog, analog-digital, analog-analog <- format: data-signal used to represent the data.

_______ provides synchronization without increasing the number of bits. a) Analog to Digital b) Line coding c) Digital to Analog d) None of the mentioned

b) Line coding. Remember we don't have a start and stop, so we are not sending extra bits.

Deadline-driven constraints are called: a) Reality-time constraints b) Real-time constraints c) Real-data constraints d) None of above

b) Real-time constraints

How many bits does a 32-bit processor can access? a) 32-bit char b) 32-bit word c) 32-bit double d) 32-bit double word

b) 32-bit word

A negative logic is a type of logic where the voltage representing FALSE is less than the voltage representing TRUE. a) TRUE b) FALSE

b) FALSE

A running Task Cannot be preempted by a higher priority task or ISR a) TRUE b) FALSE

b) FALSE

In cooperative scheduling, the execution of a process may be stopped if a higher priority process requires service a) TRUE b) FALSE

b) FALSE.

Byte ACKNOWLEDGE are the handshake signals in SPI (or SSI) a) TRUE b) FALSE

b) FALSE. ACK is I2C

In preemptive scheduling, once a process has been scheduled for execution, it runs to completion a) TRUE b) FALSE

b) FALSE. Higher priorities will run and some tasks may never finish. Cooperative will run until finished.

Registers (e.g., R0, R1 ...) in ARM architecture have dedicated address in the memory map a) TRUE b) FALSE

b) FALSE. None of the registers in the ARM have a dedicated address in memory. registers are a part of the cpu and store data etc, but they don't have specific adds. Port Registers have addresses, but CPU registers don't

A system is said to be Real Time if it is required to complete its work and deliver its services at variable times: a) TRUE b) FALSE

b) FALSE. Real Time uses fixed time bc they have to be deterministic and complete their tasks at fixed times.

To synchronize one computer to another, in UART protocol the START bit is needed, STOP bit must be one bit always. a) TRUE b) FALSE

b) FALSE. Stop bit can be 1 or 2 bits.

Hard real-time — systems where deadlines are important but which will still function correctly if deadlines are occasionally missed a) TRUE b) FALSE

b) FALSE. This is a description of soft real time. Hard Real Time tasks can never be missed.

In UART, The TX START signal goes to logic ONE to indicate the start of a transmission a) TRUE b) FALSE

b) FALSE. Tx START goes to 0.

To synchronize one computer to another, in UART protocol the START bit is needed, but the STOP bit is optional a) TRUE b) FALSE

b) FALSE. We need both START and STOP, 2 STOPs is optional but you need at least 1.

In ARM4 Cortex Architecture, Hardware automatically disable interrupts during the execution of the ISR. a) TRUE b) FALSE

b) FALSE. We use nested vector interrupt control in ARM, which allows higher priority ISRs to occur within an ISR.

Which of the following is the most commonly used buffer in the serial porting? a) LIFO b) FIFO c) FILO d) LILO

b) FIFO

Which scheduler takes their designs at configuration time? a) preemptive scheduler b) non preemptive scheduler c) dynamic scheduler d) static scheduler

d) static scheduler (we set it upfront at compile time). execution rate, schedule mechanism, etc. We can allow the execution rate to be changed later on, but it's not recommended bc system might not be deterministic. Nonpreemptive or preemptive doesn't matter here.