Week 4 CICS 620 Jones

If either the control unit or the channel is busy with another I/O, then the reconnection attempt fails and the device must rotate one whole revolution before it can attempt to reconnect

RPS miss

These levels of RAID make use of an independent access technique meaning each member disk operates independently, so that separate I/O requests can be satisfied in parallel)

RAID 4 to 6

This level of RAID distributes the parity strips across all disks

RAID 5

External memory

consists of peripheral storage devices, such as disk and tape, that are accessible to the processor via I/O controllers.

Access Time, Memory cycle time, and Transfer rate

Three performance parameters

Programmed, Interrupt-driven, and Direct memory access (DMA)

Three techniques for I/O operations

The most recent, and fastest, peripheral connection technology to become available for general-purpose use

Thunderbolt

the time required for the transfer is the ____.

Transfer time

1. The data insertion step includes a relatively large fixed cost, whether one or thousands of copies of a particular ROM are fabricated. 2. There is no room for error. If one bit is wrong, the whole batch of ROMs must be thrown out.

Two problems with ROM.

L1 Internal Cache designated as level 1 L2 External cache designated as Level 2

Two-level cache:

Capacity

Typically expressed in terms of bytes (1 byte = 8 bits) or words

type of widely used peripheral device that is controlled by a root host controller, which attaches to devices to create a local network with a hierarchical tree topology

Universal Serial Bus

Dirty bit

Use bit associated with the line

Physical Characteristics of data Storage

Volatile Memory, Nonvolatile memory, Magnetic-surface memories, Semiconductor memory, and Nonerasable memory.

1. If the old block in the cache has not been altered, then it may be overwritten with a new block without first writing out the old block 2. If at least one write operation has been performed on a word in that line of the cache, then main memory must be updated by writing the line of cache out to the block of memory before bringing in the new block

When a block that is resident in the cache is to be replaced, there are two cases to consider

is the predominant wireless Internet access technology

Wi-Fi

These are used in sealed drive assemblies that are almost free of contaminants. They are designed to operate closer to the disk's surface than conventional rigid disk heads, thus allowing greater data density. The head is actually an aerodynamic foil that rests lightly on the platter's surface when the disk is motionless

Winchester Disks and Head

1. more than one device may have access to main memory 2. A more complex problem occurs when multiple processors are attached to the same bus and each processor has its own local cache. Then, if a word is altered in one cache, it could conceivably invalidate a word in other caches.

Write Policy: There are two problems to contend with:

Random Access

1. Each addressable location in memory has a unique, physically wired-in addressing mechanism 2. The time to access a given location is independent of the sequence of prior accesses and is constant. 3. Any location can be selected at random and directly addressed and accessed. 4. Main memory and some cache systems are random access. Organization (the physical arrangement of bits to form words) is a key design issue

Associative

1. This is a random access type of memory that enables one to make a comparison of desired bit locations within a word for a specified match, and to do this for all words simultaneously. 2. Thus, a word is retrieved based on a portion of its contents rather than its address. 3. Each location has its own addressing mechanism, and retrieval time is constant independent of location or prior access patterns. Cache memories may employ associative access.

Direct Access

1. involves a shared read-write mechanism. 2. individual blocks or records have a unique address based on physical location. 3. Access time is variable

Split Caches

A ___ ___ has one cache dedicated to instructions and the other dedicated to data. Both exist at the same level, typically as two L1 caches. Trend is towards this cache at the L1

Disk Cache

A portion of main memory can be used as a buffer to hold data temporarily that is to be read out to disk.

Cache Coherency

A system that prevents caches from containing in-valid data maintains what?

Magnetic-surface memories

A type of Nonvolatile Memory

The sum of the seek time, if any, and the rotational delay equals the ______ which is the time it takes to get into position to read or write.

Access time

Hardware Transparency

Additional hardware is used to ensure that all updates to main memory via cache are reflected in all caches. Thus, if one processor modifies a word in its cache, this update is written to main memory. In addition, any matching words in other caches are similarly updated.

Unified cache

Advantages of a ____ cache is a higher hit rate because it balances the load between instruction and data fetches automatically. Trend is towards this cache at higher levels than L1

Cache

Another form of internal memory

Bus watching with write through, Hardware Transparency, and Non-cacheable memory

Approaches to Cache coherency

Multiple interrupt lines, software poll, Daisy chain, and bus arbitration

Categories of device identification

A form of semiconductor memory that can be reprogrammed rapidly. It is the intermediate between EPROM and EEPROM in both cost and functionality. It also uses an electrical erasing technology but it does not provide byte-level erasure.

Flash Memory

Type of external device that is Suitable for communicating with remote devices

Communication (I/O module)

is appropriate for the distribution of large amounts of data to a large number of users.

Compact Disk Read-Only Memory (CD-ROM)

Is rotating the disk at a fixed speed. This allows individual blocks of data on the magnetic disk to be directly addressed by track and sector.

Constant Angular velocity

The two forms of Ram used in Computers

DRAM and SRAM

Is when data coming from the main memory is sent to an I/o Module at a rapid burst, this occurs to change the data rate to fit the peripheral device's ability

Data buffering

This communication involved commands, status information, and data.

Device communication

A disk drive need not read all the sectors on a disk sequentially to get to the desired one. It must only wait for the intervening sectors within one track and can make successive accesses to any track. This is known as ___.

Direct-access device

Disk Cache improves performance by?

Disk writes are clustered. Instead of many small transfers of data, we have a few large transfers of data. This improves disk performance and minimizes processor involvement. Some data destined for write-out may be referenced by a program before the next dump to disk. In that case, the data are retrieved rapidly from the software cache rather than slowly from the disk.

a newer version of SDRAM that provides several features that dramatically increase the data rate in three ways. 1. First, the data transfer is synchronized to both the rising and falling edge of the clock, rather than just the rising edge. 2 Second, it uses higher clock rate on the bus to increase the transfer rate. 3. Third, a buffering scheme is used

Double Data Rate SDRAM (DDR SDRAM)

Type of RAM that is made with cells that store data as charge on capacitors. They also require periodic charge refreshing to maintain data storage

Dynamic RAM (DRAM)

a small, flexible platter and the least expensive type of disk where the head mechanism actually comes into physical contact with the medium during a read or write operation.

Floppy Disk

Bus watching with write through

Each cache controller monitors the address lines to detect write operations to memory by other bus masters. If another master writes to a location in shared memory that also resides in the cache memory, the cache controller invalidates that cache entry. This strategy depends on the use of a write-through policy by all cache controllers. This process is known as

Form of Read Mostly Memory that can be written into at any time without erasing prior contents; only the byte or bytes addressed are updated.

Electrically Erasable Programmable read-only memory (EEPROM)

Form of Read Mostly memory that is read and written electrically, as with PROM. However, before a write operation, all the storage cells must be erased to the same initial state by exposure of the packaged chip to ultraviolet radiation. This is more expensive than PROM but it has the advantage of the multiple update capability.

Erasable programmable read-only memory (EPROM)

is the predominant wired networking technology that began as an experimental bus-based 3-Mbps system

Ethernet

Secondary or auxiliary Memory

External, nonvolatile memory is also referred to as _____ or _____. Used to store program and data files and are usually visible to the programmer only in terms of files and records, as opposed to individual bytes or words.

Relationship between access time, capacity, and cost

Faster access time, greater cost per bit Greater capacity, smaller cost per bit Greater capacity, slower access time

Was developed as an alternative to small computer system interface (SCSI) to be used on smaller systems, such as personal computers, workstations, and servers.

FireWire Serial Bus

For applications to experience a high transfer rate, two requirements must be met.

First, a high transfer capacity must exist along the entire path between host memory and the individual disk drives. The second requirement is that the application must make I/O requests that drive the disk array efficiently

In this kind of disk there one read-write head per track

Fixed-head disk

Is permanently mounted in the disk drive; the hard disk in a personal computer is an example of this.

Non-removable disk

Internal Memory: Unit of Transfer

For main memory, this is the number of bits read out of or written into memory at a time.

A parity check

Hamming Code

Type of Failure that is a permanent physical defect so that the memory cell or cells affected cannot reliably store data but become stuck at 0 or 1 or switch erratically between 0 and 1.

Hard Failure

Two categories of Error

Hard Failure and Soft Error

A magnetic disk provides very high bit density and very low cost per bit, with relatively slow access times. It is the traditional choice for external storage as part of the memory hierarchy.

Hard disk

Rom is created like any other integrated circuit chip, with the data actually wired into the chip as part of the fabrication process

How is ROM created?

Type of external device that is Suitable for communicating with the computer user

Human readable

The I/O command that is Used to activate a peripheral and tell it what to do

I/O command Control

The I/O command that Causes the I/O module to obtain an item of data from the peripheral and place it in an internal buffer

I/O command Read

The I/O command that is Used to test various status conditions associated with an I/O module and its peripherals.

I/O command Test

The I/O command that Causes the I/O module to take an item of data (byte or word) from the data bus and subsequently transmit that data item to the peripheral.

I/O command Write

Control, test, read, write

I/O commands

to issue an I/O command to a module and then go on to do some other useful work. The I/O module will then interrupt the processor to request service when it is ready to exchange data with the processor.

I/O interrupt process

1. Interface to the processor and memory via the system bus or central switch 2. Interface to one or more peripheral devices by tailored data links

I/O modules major functions

Expanded Storage

IBM mainframes include a form of internal memory known as ______.

Internal Memory: Addressable Units

In some systems, the _______ ____ is the word. However, many systems allow addressing at the byte level. In any case, the relationship between the length in bits A of an address and the number N of addressable units is 2A = N

Volatile Memory

In this type of memory information decays naturally or is lost when electrical power is switched off

Nonvolatile memory

In this type of memory information once recorded remains without deterioration until deliberately changed; no electrical power is needed to retain information.

Nonerasable memory

In this type of memory, memory cannot be altered, except by destroying the storage unit. This type must also be nonvolatile out of necessity.

Memory Hierarchy

Inboard memory, Outboard storage, Off-line storage

is an I/O specification aimed at the high-end server market

InfiniBand

Blocks on the tape are separated by gaps referred to as _____.

Inter-record gaps

Unit of transfer

Is equal to the number of electrical lines into and out of the memory module

Issues with ____ ___ 1. Determining which device issued the interrupt 2. If multiple interrupts occur how does the processor decide which one to process

Issues with Interrupt I/o

When the memory Hierarchy is implemented

It 1. Decreases cost per bit 2. Increases Capacity 3. Increasing access time 4. Decreasing frequency of access of the memory by the processor

type of flash that is best suited to storing programs and static application data in embedded systems

Nor Flash

Key Characteristics of Computer Memory Systems

Location, Capacity, Unit Transfer, Access Method, Performance, Physical Type, Physical Characteristics, and Organization

Type of external device that is Suitable for communicating with equipment

Machine Readable

is a circular platter constructed of nonmagnetic material, called the substrate, coated with a magnetizable materia and they are the foundation of external memory on virtually all computer systems

Magnetic Disk

Data on the ____ are structured as a number of parallel tracks running lengthwise

Magnetic Tape

DRAM is simpler to build, smaller, less expensive, and tend to be favored for large memory requirements. It is often used in main memory. SRAM: is faster and used for cache memory

Main differences between DRAM and SRAM

Control and timing, Processor communication, device communication, data buffering, and error detection are thee major fuctions for an ___.

Major functions for an I/O module

External memory subsystem

Memory accessible by the processor via an I/O module

Internal memory system

Memory directly accessible by the processor and is often equated with main memory

Sequential Access

Memory is organized into units of data, called records. Access must be made in a specific linear sequence. Access time is variable

Semiconductor memory

Memory on integrated circuits that may be either volatile or nonvolatile

In this kind of disk there is only one read-write head

Movable-head disk

modern hard disk systems use this technique where the surface is divided into a number of concentric zones (16 is typical). This allows for greater overall storage capacity.

Multiple zone recording

flash that has characteristics intermediate between DRAM and hard disks

NAND Flash

When this is applied the disk can have narrower tracks and therefore greater data density

Narrower head

Non-cacheable memory

Only a portion of main memory is shared by more than one processor, and this is designated as non-cacheable. In such a system, all accesses to shared memory are cache misses, because the shared memory is never copied into the cache. The non-cacheable memory can be identified using chip-select logic or high-address bits.

The process of storing data one byte at a time, with an additional parity bit as the ninth track corresponding to a digital word or double word

Parallel recording

an external device connected to an I/o module

Peripheral device

As with the disk, data are read and written in contiguous blocks, called ______

Physical Records

1. A read request can be serviced by either of the two disks that contains the requested data, whichever one involves the minimum seek time plus rotational latency 2. A write request requires that both corresponding strips be updated, but this can be done in parallel 3. Recovery from a failure is simple

Positive aspects to this RAID 1 organization:

Command decoding, Data, Status reporting, and address recognition

Processor communication components

This type of ROM is used when only a small number of ROMs with a particular memory content is needed. It is the less expensive alternative, nonvolatile, and may be written into only once.

Programmable ROM (PROM)

RAID level for high DATA transfer Capacity and for High I/O Request Rate

RAID 0

These levels of RAID do not support the third characteristic: Redundant disk capacity

RAID 0 and RAID 1

Unlike the other RAID levels this level achieves redundancy by the simple expedient of duplicating all the data.

RAID 1

This level of RAID make use of a parallel access technique and data striping.

RAID 2

This level of RAID requires only a single redundant disk, no matter how large the disk array

RAID 3

The most common type of semiconductor memory. Memory designated as this has the capabilities to both read data from the memory and to write new data into the memory easily and rapidly. This term is also volatile.

Random-access memory (RAM).

This variation of read-only memory is useful for applications in which read operations are far more frequent than write operations but for which nonvolatile storage is required. It's three forms are EPROM, EEPROM, and Flash Memory.

Read Mostly Memory purpose and forms

Type of memory that contains a permanent pattern of data that cannot be changed, is Nonvolatile, and it is possible to read this type of memory but not to write new data into it.

Read only Memory (ROM)

Consists of seven levels, zero through six. These levels do not imply a hierarchical relationship but designate different design architectures that share three common characteristics: 1. It is a set of physical disk drives viewed by the operating system as a single logical drive. 2. Data is organized using striping 3. Redundant disk capacity is used to store parity information, which guarantees data recoverability in case of a disk failure

Redundant Array of Independent Disks (RAID)

Memory Location

Refers to whether memory is internal and external to the computer

Is a type of disk that can be removed and replaced with another disk. Examples: Floppy disks and ZIP cartridge disks

Removable disk

The time it takes for the beginning of the sector to reach the head

Rotational Delay or Rotational latency

On a movable-head system, the time it takes to position the head at the track

Seek time

In a memory cell, this selects a memory cell for a read or write operation

Select Terminal

ROM, DRAM, and SRAM memories

Semiconductor Main Memory subsystems

Read-only memory (ROM)

Semiconductor memory of the Nonerasable memory type

Methods of Accessing Units of Data

Sequential Access, Direct Access, Random Access, and Associative

in which data are laid out as a sequence of bits along each track, as is done with magnetic disks

Serial Recording

The typical recording technique used in serial tapes. In this technique, when data are being recorded, the first set of bits is recorded along the whole length of the tape. When the end of the tape is reached, the heads are repositioned to record a new track, and the tape is again recorded on its whole length, this time in the opposite direction.

Serpentine recording

1. They exhibit two stable (or semistable) states, which can be used to represent binary 1 and 0. 2. They are capable of being written into (at least once), to set the state. 3. They are capable of being read to sense the state.

Shared properties of semiconductor memory cells

Write Through

Simplest Technique, all write operations are made to main memory as well as to the cache, ensuring that main memory is always valid. Main disadvantage of this technique is that it generates substantial memory traffic and may create a bottleneck.

Was once a common standard for connecting peripheral devices

Small computer system interface (SCSI)

Type of Error that is a random, nondestructive event that alters the contents of one or more memory cells without damaging the memory. Can be caused by power supply problems or alpha particles

Soft Error

Type of RAM that uses the same logic elements used in the processor. Volatile and provides rapid access time, but is the most expensive and the least dense (bit density). Making it suitable for cache memory. It is Cheaper, denser, and slower than SRAM

Static RAM (SRAM)

Mainly provides current status information. It May also function as a control register to accept detailed control information from the processor

Status register in an I/O module

Process in RAID Where Data is distributed across the physical drives of an array

Striping

A circular platter constructed of nonmagnetic material

Substrate

One of the most widely used forms of DRAM and it exchanges data with the processor that is synchronized to an external clock signal and running at the full speed of the processor/memory bus without imposing wait states.

Synchronous DRAM (SDRAM)

Internal memory: Word

The "natural" unit of organization of memory

On-chip caches

The ___ ___ ___ reduces the processor's external bus activity and speeds up execution time and increases overall system performance

Semiconductor memory

The basic element of a ____ ___ is the memory cell

Locality of Reference [DENN68]

The basis for the validity of condition "Decreasing frequency of access of the memory by the processor" iz principle known as ______

In a memory cell, this indicates read or write

The control terminal

How much? How Fast? How expensive?

The design constraints on a computer's memory can be summed up by three questions

A conducting coil that retrieves data on the magnetic disk. In many systems there are two of these. One that reads and one that writes. The platter rotates beneath this

The head for a magnetic disk

is that it eliminates contention for the cache between the instruction fetch/decode unit and the execution unit.

The key advantages of the Split Cache design

Human readable, Machine readable, and communication

Three categories of External Devices

Forms of memory

The most common today are semiconductor memory, magnetic surface memory, optical, and magneto-optical.

Capacity, access time, and cost

The trade-off among the three key characteristics of memory

Capacity and Performance

The two most important characteristics of memory

Transfer Rate

This is the rate at which data can be transferred into or out of a memory unit. For random-access memory, it is equal to 1/(cycle time).

Memory Cycle Time for random-access memory

consists of the access time plus any additional time required before a second access can commence. This additional time may be required for transients to die out on signal lines or to regenerate data if they are read destructively. Note that this is concerned with the system bus, not the processor.

Access Time (latency) for Non-random-access memory

is the time it takes to position the read-write mechanism at the desired location.

Stored addressing information

is used to separate records and assist in the retrieval process

Write Back

minimizes memory writes, updates are made only in the cache, when a block is replaced, it is written back to main memory if and only if the dirty bit is set The problem is that portions of main memory are invalid, and hence accesses by I/O modules can be allowed only through the cache. Causing complex circuitry and a potential bottleneck

When the seek command has been issued, the channel is released to handle other I/O operations. When the seek is completed, the device determines when the data will rotate under the head. As that sector approaches the head, the device tries to reestablish the communication path back to the host.

rotational positional sensing (RPS)

A tap drive requires the tape head to read all records before the desired record. For instance, If the tape head is positioned at record 1, then to read record N, it is necessary to read physical records 1 through N -1, one at a time. This is known as __.

sequential-access device

To achieve greatest performance...

the memory must be able to keep up with the processor.

Access Time (latency) for Random-access memory

the time it takes to perform a read or write operation, that is, the time from the instant that an address is presented to the memory to the instant that data have been stored or made available for use.