[1] Digital Electronics

(43)10 = (01000011)2 . 20. The circuit of the given figure realizes the function A. Y = (A + B) C + DE B. Y = A + B + C + D + E C. AB + C +DE D. AB + C(D + E)

A

17. The expression Y = M (0, 1, 3, 4) is A. POS B. SOP C. Hybrid D. none of the above

A

18. An 8 bit DAC has a full scale output of 2 mA and full scale error of ± 0.5%. If input is 10000000 the range of outputs is A. 994 to 1014 μA B. 990 to 1020 μA C. 800 to 1200 μA D. none of the above

A

2. 2's complement of binary number 0101 is A. 1011 B. 1111 C. 1101 D. 1110

A

25. In a ripple counter, A. whenever a flip flop sets to 1, the next higher FF toggles B. whenever a flip flop sets to 0, the next higher FF remains unchanged C. whenever a flip flop sets to 1, the next higher FF faces race condition D. whenever a flip flop sets to 0, the next higher FF faces race condition

A

26. A 12 bit ADC is used to convert analog voltage of 0 to 10 V into digital. The resolution is A. 2.44 mV B. 24.4 mV C. 1.2 V D. none of the above

A

29. If the functions w, x, y, z are as follows. w = R + PQ + RS , x = PQR S + PQR S + PQ R S Then A. w = z x = z B. w = z, x = y C. w = y D. w = y = z

A

39. A counter type A/D converter contains a 4 bit binary ladder and a counter driven by a 2 MHz clock. Then conversion time A. 8 μ sec B. 10 μ sec C. 2 μ sec D. 5 μ sec

A

40. The hexadecimal number (3E8)16 is equal to decimal number A. 1000 B. 982 C. 768 D. 323

A

43. For the K map in the given figure the simplified Boolean expression is A. A C + A D + ABC B. A C + A D + ABC C. A C + A D + ACD D. A C + A D + AB C

A

47. In a BCD to 7 segment decoder the minimum and maximum number of outputs active at any time is A. 2 and 7 B. 3 and 7 C. 1 and 6 D. 3 and 6

A

49. Maxterm designation for A + B + C is A. M0 B. M1 C. M3 D. M4

A

50. 1's complement of 11100110 is A. 00011001 B. 10000001 C. 00011010 D. 00000000

A

1. The resolution of an n bit DAC with a maximum input of 5 V is 5 mV. The value of n is A. 8 B. 9 C. 10 D. 11

C

44. A memory system of size 16 k bytes is to be designed using memory chips which have 12 address lines and 4 data lines each. The number of such chips required to design the memory system is A. 2 B. 4 C. 8 D. 18

C

8. A decade counter skips A. binary states 1000 to 1111 B. binary states 0000 to 0011 C. binary states 1010 to 1111 D. binary states 1111 to higher

C

11. For the gate in the given figure the output will be A. 0 B. 1 C. A D. A

D

12. In the expression A + BC, the total number of minterms will be A. 2 B. 3 C. 4 D. 5

D

23. A JK flip flop has tpd= 12 ns. The largest modulus of a ripple counter using these flip flops and operating at 10 MHz is A. 16 B. 64 C. 128 D. 256

D

41. The number of distinct Boolean expression of 4 variables is A. 16 B. 256 C. 1024 D. 65536

D

13. The circuit in the given figure is A. positive logic OR gate B. negative logic OR gate C. negative logic AND gate D. positive logic AND gate

B

28. A full adder can be made out of A. two half adders B. two half adders and a OR gate C. two half adders and a NOT gate D. three half adders

B

3. An OR gate has 4 inputs. One input is high and the other three are low. The output A. is low B. is high C. is alternately high and low D. may be high or low depending on relative magnitude of inputs

B

31. Minimum number of 2-input NAND gates required to implement the function F = (x + y) (Z + W) is A. 3 B. 4 C. 5 D. 6

B

33. A carry look ahead adder is frequently used for addition because A. it costs less B. it is faster C. it is more accurate D. is uses fewer gates

B

34. The counter in the given figure is A. Mod 3 B. Mod 6 C. Mod 8 D. Mod 7

B

35. In register index addressing mode the effective address is given by A. index register value B. sum of the index register value and the operand C. operand D. difference of the index register value and the operand

B

36. 7BF16 = __________ 2 A. 0111 1011 1110 B. 0111 1011 1111 C. 0111 1011 0111 D. 0111 1011 0011

B

37. For the minterm designation Y = ∑ m (1, 3, 5, 7) the complete expression is A. Y = A BC + A B C B. Y = A B C + A B C + ABC + A BC C. Y = A B C + A B C + ABC + A BC D. Y = A B C + ABC + A BC + A BC

B

38. Zero suppression is not used in actual practice. A. True B. False

B

4. Decimal number 10 is equal to binary number A. 1110 B. 1010 C. 1001 D. 1000

B

46. AB + AB = A. B B. A C. 1 D. 0

B

5. Both OR and AND gates can have only two inputs. A. True B. False

B

6. A device which converts BCD to seven segment is called A. encoder B. decoder C. multiplexer D. none of these

B

= xyz + xyw = minimum no. of 2 input NAND gate. 32. Which device has one input and many outputs? A. Multiplexer B. Demultiplexer C. Counter D. Flip flop

B

If there is no error, output = = 1004μA. Maximum error = Hence range of output 994 to 1014 μA. 19. Decimal 43 in hexadecimal and BCD number system is respectively. A. B2, 01000011 B. 2B, 01000011 C. 2B, 00110100 D. B2, 01000100

B

Y = (A + B)C + DE. 21. An AND gate has two inputs A and B and one inhibit input 3, Output is 1 if A. A = 1, B = 1, S = 1 B. A = 1, B = 1, S = 0 C. A = 1, B = 0, S = 1 D. A = 1, B = 0, S = 0

B

14. Which of the following is non-saturating? A. TTL B. CMOS C. ECL D. Both (a) and (b)

C

30. The output of a half adder is A. SUM B. CARRY C. SUM and CARRY D. none of the above

C

9. BCD input 1000 is fed to a 7 segment display through a BCD to 7 segment decoder/driver. The segments which will lit up are A. a, b, d B. a, b, c C. all D. a, b, g, c, d

C

45. In a 7 segment display, LEDs b and c lit up. The decimal number displayed is A. 9 B. 1 C. 3 D. 1

D

48. A three state switch has three outputs. These are A. low, low and high B. low, high, high C. low. floating, low D. low, high, floating

D

7. In 2's complement representation the number 11100101 represents the decimal number A. +37 B. -31 C. +27 D. -27

D

10. A ring counter with 5 flip flops will have A. 5 states B. 10 states C. 32 states D. infinite states

A

15. The number of digits in octal system is A. 8 B. 7 C. 9 D. 10

A

16. The access time of a word in 4 MB main memory is 100 ms. The access time of a word in a 32 kb data cache memory is 10 ns. The average data cache bit ratio is 0.95. The efficiency of memory access time is A. 9.5 ns B. 14.5 ns C. 20 ns D. 95 ns

B

22. The greatest negative number which can be stored is 8 bit computer using 2's complement arithmetic is A. - 256 B. - 128 C. - 255 D. - 127

B

27. For the truth table of the given figure Y = A. A + B + C B. A + BC C. A D. B

D

42. The fixed count that should be used so that the output register will represent the input for a 6 bit dual slope A/D converter uses a reference of -6v and a 1 MHz clock. It uses a fixed count of 40 (101000). A. 000110 B. 0010 C. 1111 D. 011101

A

Modulus = 28 = 256. 24. The basic storage element in a digital system is A. flip flop B. counter C. multiplexer D. encoder

A