Architecture

terabyte

10^12 or 2^40 bytes

petabyte

10^15 or 2^50 bytes

servers

A class of computers composed of hundred to thousand processors and terabytes of memory and having the highest performance and cost

embedded computers

A computer used to running one predetermined application or collection of software

machine language

Binary language that the processor can understand

1.2.4 2 microseconds from cache==> 20 microseconds from DRAM. 1.2.5 20 microseconds from DRAM ==> 2 seconds from magnetic disk. 1.2.6 20 microseconds from DRAM=> 2 ms from flash memory.

Cache DRAM Flash Memory Magnetic Disk a. 5 ns 50 ns 5 μs 5 ms b. 7 ns 70 ns 15 μs 20 ms 1.2.4 Find how long it takes to read a file from a DRAM if it takes 2 microseconds from the cache memory. 1.2.5 Find how long it takes to read a file from a disk if it takes 2 microseconds from the cache memory. 1.2.6 Find how long it takes to read a file from a flash memory if it takes 2 microseconds from the cache memory.

instruction

Commands that the processors understand

supercomputers

Computer used to run large problems and usually accessed via a network

1.2.1 8 bits x 3 colors = 24 bits/pixel = 4 bytes/pixel. 1280 x 800 pixels = 1,024,000 pixels. 1,024,000 pixels x 4 bytes/pixel = 4,096,000 bytes (approx 4 Mbytes). 1.2.2 2 GB = 2000 Mbytes. No. frames = 2000 Mbytes/4 Mbytes = 500 frames. 1.2.3 Network speed: 1 gigabit network ==> 1 gigabit/per second = 125 Mbytes/second. File size: 256 Kbytes = 0.256 Mbytes. Time for 0.256 Mbytes = 0.256/125 = 2.048 ms.

Configuration Resolution Main Mem Ethernet Network a. 1 640 × 480 2 GB 100 Mbit 2 1280 × 1024 4 BG 1 Gbit b. 1 1024 × 768 2 GB 100 Mbit 2 2560 × 1600 4 GB 1 Gbit 1.2.1 For a color display using 8 bits for each of the primary colors (red, green, blue) per pixel, what should be the minimum size in bytes of the frame buffer to store a frame? 1.2.2 How many frames could it store, assuming the memory contains no other information? 1.2.3 If a 256 Kbytes file is sent through the Ethernet connection, how long it would take?

1.7.4 C = P/V^2 x clockrate 80286: C = 0.0105 x 10^-6 80386: C = 0.01025 x 10^-6 80486: C = 0.00784 x 10^-6 Pentium: C = 0.00612 x 10^-6 Pentium Pro: C = 0.0133 x 10^-6 Pentium 4 Willamette: C = 0.0122 x 10^-6 Pentium 4 Prescott: C = 0.00183 x 10^-6 Core 2: C = 0.0294 x 10^-6 1.7.5 3.3/1.75 = 1.78 (Pentium Pro to Pentium 4 Willamette) 1.7.6 Pentium to Pentium Pro: 3.3/5 = 0.66 Pentium Pro to Pentium 4 Willamette: 1.75/3.3 = 0.53 Pentium 4 Willamette to Pentium 4 Prescott: 1.25/1.75 = 0.71 Pentium 4 Prescott to Core 2: 1.1/1.25 = 0.88 Geometric mean = 0.68

Consider the following values for voltage in each generation. Processor Voltage 80286 (1982) 5 80386 (1985) 5 80486 (1989) 5 Pentium (1993) 5 Pentium Pro (1997) 3.3 Pentium 4 Willamette (2001) 1.75 Pentium 4 Prescott (2004) 1.25 Core 2 Ketsfield (2007) 1.1 1.7.4 Find the average capacitive loads, assuming a negligible static power consumption. 1.7.5 Find the largest relative change in voltage between generations. 1.7.6 Find the geometric mean of the voltage ratios in the generations since the Pentium.

1.3.1 P2 has the highest performance performance of Pl (instructions/sec)= 2 x 10^9/1.5 = 1.33 x 10^9 performance of P2 (instructions/sec)= 1.5 x 10^9/1.0 = 1.5 x 10^9 performance of P3 (instructions/sec)= 3 x 10^9/2.5 = 1.2 x 10^9 1.3.2 No. cycles = time x clock rate cycles(Pl) = 10 x 2 x 10^9 = 20 x 10^9 s cycles(P2) = 10 x 1.5 x 10^9 = 15 x 10^9 s cycles(P3) = 10 x 3 x 10^9 = 30 x 10^9 s time= (No. instr. x CPI)/clock rate, then No. instructions= No. cycles/CPI instructions(Pl) = 20 x 109/1.5 = 13.33 x 109 instructions(P2) = 15 x 109/1 = 15 x 109 instructions(P3) = 30 x 109/2.5 = 12 x 109 1.3.3 time new = time old X 0.7 = 7 s CPI= CPI x 1.2, then CPI(Pl) = 1.8, CPI(P2) = 1.2, CPI(P3) = 3 f = No. instr. x CPI/time, then f(Pl) = 13.33 X 109 X 1.8/7 = 3.42 GHz f(P2) = 15 X 109 X 1.2/7 = 2.57 GHz f(P3) = 12 x 109 x 3/7 = 5.14 GHz

Consider three different processors P1, P2, and P3 executing the same instruction set with the clock rates and CPIs given in the following table. Processor Clock Rate CPI a. P1 3 GHz 1.5 P2 2.5 GHz 1.0 P3 4 GHz 2.2 b. P1 2 GHz 1.2 P2 3 GHz 0.8 P3 4 GHz 2.0 1.3.1 Which processor has the highest performance expressed in instructions per second? 1.3.2 If the processors each execute a program in 10 seconds, find the number of cycles and the number of instructions. 1.3.3 We are trying to reduce the time by 30% but this leads to an increase of 20% in the CPI. What clock rate should we have to get this time reduction?

low-end servers

Desktop computer without a screen or keyboard usually accessed via a networ

1.3.4 IPC = 1/CPI = No. instr./(time x clock rate) IPC(Pl) = 1.42 IPC(P2) = 2 IPC(P3) = 3.33 1.3.5 Time new/Time old = 7/10 = 0.7. So f new = f old/0.7 = 1.5 GHz/0.7 = 2.14 GHz 1.3.6 Time new/Time Old = 9/10 = 0.9. So Instructions new = Instructions old x 0.9 = 30 x 109 x 0.9 = 27 x 109

For problems below, use the information in the following table. Processor Clock Rate No. Instructions Time a. P1 3 GHz 20.00E+09 7 s P2 2.5 GHz 30.00E+09 10 s P3 4 GHz 90.00E+09 9 s b. P1 2 GHz 20.00E+09 5 s P2 3 GHz 30.00E+09 8 s P3 4 GHz 25.00E+09 7 s 1.3.4 Find the IPC (instructions per cycle) for each processor. 1.3.5 Find the clock rate for P2 that reduces its execution time to that of P1. 1.3.6 Find the number of instructions for P2 that reduces its execution time to that of P3.

2.19.1 a. compare: addi $sp, $sp , -4 sw $ra , 0($sp) add $s0, $a0 , $0 add $s1, $a1, $0 jal sub addi $t1, $0, 1 beq $v0, $0, exit slt $t2, $0, $v0 bne $t2, $0, exit addi $t1, $0, $0 exit: add $v0, $t1, $0 lw $ra , 0($sp) addi $sp , $sp , 4 jr $ra sub: sub $v0, $a0, $al jr $ra b. fib_iter : addi $sp , $sp, -16 sw $ra , 12($sp) sw $s0, 8($sp) sw $s1, 4($sp) sw $s2, 0($sp) add $s0 , $a0, $0 add $s1, $a1, $0 add $s2, $a2, $0 add $v0, $s1, $0 bne $s2 , $0 , exit add $a0, $s0, $sl add $al, $s0, $0 add $a2 , $s2, -1 ja l fib_iter exi t : lw $s2, 0($sp) lw $s1, 4($sp) lw $s0, 8($sp) lw $ra , 12($sp) addi $sp , $sp, 16 jr $ra 2.19.2 a. compa re: addi $sp , $sp, -4 sw $ra , 0($sp) sub $t0, $a0, $a1 addi $tl, $0, 1 beq $t0, $0 , ex i t slt $t2 , $0, $t0 bne $t2, $0 , ex i t addi $tl, $0, $0 ex i t : add $v0, $tl, $0 lw $ra, 0($sp) addi $sp, $sp, 4 jr $ra b. Due to the recursive nature of the code. Not possible for the compiler to in line the function call. 2.19.3 a. after calling function compare: old $sp => 0x7ffffffc ??? $sp => -4 contents of register $ra after calling function sub: old $sp => 0x7ffffffc ??? -4 contents of register $ra $sp => -8 contents of register $ra #return to compare b. after calling function fib_iter: old $sp => 0x7ffffffc ??? -4 contents of register $ ra -8 contents of register $s0 -12 contents of register $s1 $sp => -16 contents of register $s2 2.19.4 a. f: addi $sp, $sp, -8 sw $ra, 4($sp) sw $s0, 0($sp) move $s0, $a2 jal func move $a0, $v0 move $a1, $s0 jal func lw $ra, 4($sp) lw $s0, 0($sp) addi $sp, $sp, 8 jr $ra b. f: addi $sp, $sp, -12 sw $ra, 8($sp) sw $sl, 4($sp) sw $s0, 0 ($sp) mov e $s0, $a1 mov e $sl, $a2 jal func move $a0, $s0 move $a1, $s1 mov e $s0, $v0 jal func add $v0, $v0, $s0 lw $ra, 8($sp) lw $s1, 4($sp) lw $s0, 0($sp) addi $sp, $sp, 12 jr ra 2.19.5 a. We can use the tail-call optimization for the second call to func, but then we must restore $ra and $sp before that call. We save only one instruction (jr $ra). b. We can NOT use the tail call optimization here, because the value returned from f is not equal to the value returned by the last call to func. 2.19.6 Register $ra is equal to the return address in the caller function, registers $sp and $s3 have the same values they had when function f was called, and register $t5 can have an arbitrary value. For register $t5, note that although our function f does not modify it, function func is allowed to modify it so we cannot assume anything about the of $t5 after function func has been called.

For the following problems, the table holds C code functions. Assume that the first function listed in the table is called first. You will be asked to translate these C code routines into MIPS assembly. a. int fib(int n){ if (n==0) return 0; else if (n == 1) return 1; else fib(n-1) + fib(n-2); b. int positive(int a, int b) { if (addit(a, b) > 0) return 1; else return 0; } int addit(int a, int b) { return a+b; } 2.19.1 [15] <2.8> Implement the C code in the table in MIPS assembly. What is the total number of MIPS instructions needed to execute the function? 2.19.2 [5] <2.8> Functions can often be implemented by compilers "in-line." An in-line function is when the body of the function is copied into the program space, allowing the overhead of the function call to be eliminated. Implement an "in-line" version of the the C code in the table in MIPS assembly. What is the reduction in the total number of MIPS assembly instructions needed to complete the function? Assume that the C variable n is initialized to 5. 2.19.3 [5] <2.8> For each function call, show the contents of the stack after the function call is made. Assume the stack pointer is originally at address 0x7ffffffc, and follow the register conventions as specified in Figure 2.11. The following three problems in this Exercise refer to a function f that calls another function func. The code for C function func is already compiled in another module using the MIPS calling convention from Figure 2.14. The function declaration for func is "int func(int a, int b);". The code for function f is as follows: a. int f(int a, int b, int c, int d){ return func(func(a,b),c+d); } b. int f(int a, int b, int c, int d){ if(a+b>c+d) return func(a+b,c+d); return func(c+d,a+b); } 2.19.4 [10] <2.8> Translate function f into MIPS assembly language, also using the MIPS calling convention from Figure 2.14. If you need to use registers $t0 through $t7, use the lower-numbered registers first. 2.19.5 [5] <2.8> Can we use the tail-call optimization in this function? If no, explain why not. If yes, what is the difference in the number of executed instructions in f with and without the optimization? 2.19.6 [5] <2.8> Right before your function f from Problem 2.19.4 returns, what do we know about contents of registers $t5, $s3, $ra, and $sp? Keep in mind that we know what the entire function f looks like, but for function func we only know its declaration.

cobol

High level language for business data processing

fortran

High level language for scientific computation

C

High level language used to write application and system software

2.10.4 a. 0x01004020 " b. 0x8E690004 2.10.5 a. R-type b. I-type 2.10.6 a. op=0x0, rd=0x8, rs=0x8 , rt=0x0, funct=0x0 b. op=0x23, rs=0x13, rt=0x9, imm=0x4

In the following problems, the data table contains MIPS instructions. You will be asked to translate the entries into the bits of the opcode and determine the MIPS instruction format. a. addi $t0, $t0, 0 b. sw $t1, 32($t2) 2.10.4 [5] <2.4, 2.5> For the instructions above, show the binary then hexadecimal representation of these instructions. 2.10.5 [5] <2.5> What type (I-type, R-type, J-type) instruction do the instructions above represent? 2.10.6 [5] <2.5> What is the binary then hexadecimal representation of the opcode, Rs, and Rt fields in this instruction? For R-type instructions, what is the hexadecimal representation of the Rd and funct fields? For I-type instructions, what is the hexadecimal representation of the immediate field?

2.10.1 sw $t3, 4($s0) lw $t0, 64($t0) 2.10.2 a. I-type " b. I-type 2.10.3 a. EOB0004 b. 8D080040

In the following problems, the data table contains bits that represent the opcode of an instruction. You will be asked to interpret the bits as MIPS instructions into assembly code and determine what format of MIPS instruction the bits represent. a. 0000 0010 0001 0000 1000 0000 0010 0000two b. 0000 0001 0100 1011 0100 1000 0010 0010two 2.10.1 [5] <2.5> For the binary entries above, what instruction do they represent? 2.10.2 [5] <2.5> What type (I-type, R-type, J-type) instruction do the binary entries above represent? 2.10.3 [5] <2.4, 2.5> If the binary entries above were data bits, what number would they represent in hexadecimal?

2.12.4 a. 17367056 b. 23661772 2.12.5 $t0 , $tl , $0 $tl, 12($t0) 2.12.6 a. R-type, op=0x0, rt=0x9 b. I-type, op=0x23 , rt=0x8

In the following problems, the data table contains hexadecimal values. You will be asked to determine what MIPS instruction the value represents, and find the MIPS instruction format. a. 0x01090012 b. 0xAD090012 2.12.4 [5] <2.5> For the entries above, what is the value of the number in decimal? 2.12.5 [5] <2.5> For the hexadecimal entries above, what instruction do they represent? 2.12.6 [5] <2.4, 2.5> What type (I-type, R-type, J-type) instruction do the binary entries above represent? What is the value of the op field and the rt field?

2.12.1 Type opcode rs rt rd shamt func a)R-type 6 3 3 3 5 6 total bits = 26 b)R-type 6 5 5 5 5 6 total bits = 32 2.12.2 Type opcode rs rt immed a) i-type 6 3 3 16 total bits = 28 b) i-type 6 5 5 10 total bits = 26 2.12.3 a. less registers --> less bits per instruction --> could reduce code size less registers --> more register spills --> more instructions b. smaller constants --> more lui instructions --> could increase code size smaller constants --> smaller opcodes --> smaller code size"

In the following problems, the data table contains various modifications that could be made to the MIPS instruction set architecture. You will investigate the impact of these changes on the instruction format of the MIPS architecture. a. 128 registers b. Four times as many different instructions 2.12.1 [5] <2.5> If the instruction set of the MIPS processor is modified, the instruction format must also be changed. For each of the suggested changes above, show the size of the bit fields of an R-type format instruction. What is the total number of bits needed for each instruction? 2.12.2 [5] <2.5> If the instruction set of the MIPS processor is modified, the instruction format must also be changed. For each of the suggested changes above, show the size of the bit fields of an I-type format instruction. What is the total number of bits needed for each instruction? 2.12.3 [5] <2.5, 2.10> Why could the suggested change in the table above decrease the size of an MIPS assembly program? Why could the suggested change in the table above increase the size of an MIPS assembly program?

2.5.1 a. Address Data temp = Array[3]; 12 1 Array [3] = Array[2] 8 6 Array [2] = Array[1] 4 4 Array[1] = Array[0] 0 2 Array [0] = temp; b. Address Data temp = Array[ 4]; 16 1 Array [4] = Array[0]; 12 2 Array[0] = temp ; 8 3 temp = Array[ 3]; 4 4 Array[ 3] = Array[ 1]; 0 5 Array [1] = temp; 2.5.2" a. Address Data temp = Array[ 3]; lw $t0, 12($s6) 12 1 Array [3] = Array[2]; lw $tl, 8($s6) 8 6 Array [2] = Array[1]; sw $tl, 12($s6) 4 4 Array[1] = Array[0]; lw $tl, 4($s6) 0 2 Array [0] = temp; sw $tl, 8($s6) lw $tl, 0($s6) sw $tl, 4($s6) sw $t0, 0($s6) b. Address Data temp = Array[4]; lw $t0, 16 ($s6) 16 1 Array [4]= Array[0]; lw $tl, 0($s6) 12 2 Array [0] = temp; sw $tl, 16 ($s6) 8 3 temp = Array[3]; sw $t0, 0($s6) 4 4 Array [3] = Array[1]; lw $t0, 12($s6) 0 5 Array [1]= temp; lw $tl, 4($s6) sw $tl, 12($s6) sw $t0, 4($s6) 2.5.3 a. Address Data temp = Array[3]; lw $t0, 12($s6) 12 1 Array[3] = Array[2] lw $tl, 8($s6) 8 6 Array[2] = Array[1] sw $tl, 12($s6) 4 4 Array[1] = Array[0] lw $tl, 4($s6) 0 2 Array[0] = temp ; sw $tl, 8($s6) lw $tl, 0($s6) sw $tl, 4($s6) sw $t0. 0($s6) 8 mips instructions , +1 mips instruction for every non- zero offset lw/sw pair (11mips inst.) b. Address Data temp = Array[4]; lw $t0, 16($s6) 16 1 Array [4] = Array[0]; lw $t1, 0($s6) 12 2 Array[0] = temp; sw $t1, 16($s6) 8 3 temp = Array[ 3]; sw $t0, 0($s6) 4 4 Array[ 3] = Array[1]; lw $t0, 12($s6) 0 5 Array [1] = temp; lw $t1, 4($s6) sw $tl, 12($s6) sw $t0, 4($s6) 8 mips instructions , +1 mips inst. for every non-zero offset lw/sw pair (11 mips inst.)

In the following problems, we will be investigating memory operations in the context of an MIPS processor. The table below shows the values of an array stored in memory. Assume the base address of the array is stored in register $s6 and offset it with respect to the base address of the array. a. Address Data 20 4 24 5 28 3 32 2 34 1 b. Address Data 24 2 38 4 32 3 36 6 40 1 2.5.1 [10] <2.2, 2.3> For the memory locations in the table above, write C code to sort the data from lowest to highest, placing the lowest value in the smallest memory location shown in the figure. Assume that the data shown represents the C variable called Array, which is an array of type int, and that the first number in the array shown is the first element in the array. Assume that this particular machine is a byte-addressable machine and a word consists of four bytes. 2.5.2 [10] <2.2, 2.3> For the memory locations in the table above, write MIPS code to sort the data from lowest to highest, placing the lowest value in the smallest memory location. Use a minimum number of MIPS instructions. Assume the base address of Array is stored in register $s6. 2.5.3 [5] <2.2, 2.3> To sort the array above, how many instructions are required for the MIPS code? If you are not allowed to use the immediate field in lw and sw instructions, how many MIPS instructions do you need?

operating system

Interface between user's program and hardware providing a variety of services and supervision functions

multicore processors

Microprocessors containing several processors in the same chip

desktop computers

Personal computer delivering good performance to single users at low cost.

high-level language

Portable language composed of words and algebraic expressions that must be translated into assembly language before run in a computer

compiler

Program that translates statements in high level language to assembly language

assembler

Program that translates symbolic instructions to binary instructions

system software

Software layer between the application software and the hardware that includes the operating system and the compilers

application software

Software/programs developed by the users

VHDL

Special language used to describe hardware components. VHSIC Hardware Description Language

assembly language

Symbolic representation of machine instructions

2.4.1 a. lw $s0, 16($s7) add $s0, $s0, $sl add $s0, $s0, $s2 b. lw $t0, 16($s7) lw $s0, 0($t0) sub $s0, $sl, $s0 2.4.2 a. 3 b. 3 2.4.3 a. 4 b. 4

The following problems deal with translating from C to MIPS. Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. a. f = -g - A[4]; b. B[8] = A[i-j]; 2.4.1 [10] <2.2, 2.3> For the C statements above, what is the corresponding MIPS assembly code? 2.4.2 [5] <2.2, 2.3> For the C statements above, how many MIPS assembly instructions are needed to perform the C statement? 2.4.3 [5] <2.2, 2.3> For the C statements above, how many different registers are needed to carry out the C statement?

2.6.1 a. lw $s0, 4($s7) sub $s0, $s0. $sl add $s0, $s0, $s2 b. add $t0, $s7, $sl lw $t0, 0($t0) add $t0, $t0, $s6 lw $s0, 4($t0) 2.6.2 a. 3 b. 4 2.6.3 a. 4 b. 5

The following problems deal with translating from C to MIPS. Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. Assume that the elements of the arrays A and B are 4-byte words: a. f = f + A[2]; b. B[8] = A[i] + A[j]; 2.6.1 [10] <2.2, 2.3> For the C statements above, what is the corresponding MIPS assembly code? 2.6.2 [5] <2.2, 2.3> For the C statements above, how many MIPS assembly instructions are needed to perform the C statement? 2.6.3 [5] <2.2, 2.3> For the C statements above, how many registers are needed to carry out the C statement using MIPS assembly code?

2.2.1 a. add f, f, f add f, f, i b. add f, j, 2 add f, f, g 2.2.2 a. 2 b. 2 2.2.3 a. 6 b. 5

The following problems deal with translating from C to MIPS. Assume that the variables g, h, i, and j are given and could be considered 32-bit integers as declared in a C program. a. f = g - f; b. f = i + (h - 2); 2.2.1 [5] <2.2> For the C statements above, what is the corresponding MIPS assembly code? Use a minimal number of MIPS assembly instructions. 2.2.2 [5] <2.2> For the C statements above, how many MIPS assembly instructions are needed to perform the C statement? 2.2.3 [5] <2.2> If the variables f, g, h, and i have values 1, 2, 3, and 4, respectively, what is the end value of f?

2.4.4 a. f += g + h + i + j b. f = A[1] 2.4.5 a. no change b. no change 2.4.6 a. 5 as written, 5 minimally b. 2 as written, 2 minimally

The following problems deal with translating from MIPS to C. Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. a. sll $s2, $s4, 1 add $s0, $s2, $s3 add $s0, $s0, $s1 b. sll $t0, $s0, 2 # $t0 = f * 4 add $t0, $s6, $t0 # $t0 = &A[f] sll $t1, $s1, 2 # $t1 = g * 4 add $t1, $s7, $t1 # $t1 = &B[g] lw $s0, 0($t0) # f = A[f] addi $t2, $t0, 4 lw $t0, 0($t2) add $t0, $t0, $s0 sw $t0, 0($t1) 2.4.4 [10] <2.2, 2.3> For the MIPS assembly instructions above, what is the corresponding C statement? 2.4.5 [5] <2.2, 2.3> For the MIPS assembly instructions above, rewrite the assembly code to minimize the number if MIPS instructions (if possible) needed to carry out the same function. 2.4.6 [5] <2.2, 2.3> How many registers are needed to carry out the MIPS assembly as written above? If you could rewrite the code above, what is the minimal number of registers needed?

2.6.4 f = 2i + h ; f = A[ g - 3] ; 2.6.5 $so = 110 $so = 300 2.6.6 a. Type opcode rs rt rd immed add $s0, $s0, $sl R-type 0 16 17 16 add $s0, $s3, $s2 R-type 0 19 18 16 add $s0, $s0, $s3 R-type 0 16 19 16 b. addi $s6, $s6, -20 i-type 8 22 22 -20 add $s6, $s6 , $sl R-type 0 22q 17 22 lw $s0, 8($s6) i-type 35 22 16 8

The following problems deal with translating from MIPS to C. Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. a. sub $s0, $s0, $s1 sub $s0, $s0, $s3 add $s0, $s0, $s1 b. addi $t0, $s6, 4 add $t1, $s6, $0 sw $t1, 0($t0) lw $t0, 0($t0) add $s0, $t1, $t0 2.6.4 [5] <2.2, 2.3> For the MIPS assembly instructions above, what is the corresponding C statement? 2.6.5 [5] <2.2, 2.3> For the MIPS assembly above, assume that the registers $s0, $s1, $s2, and $s3 contain the values 0x0000000a, 0x00000014, 0x0000001e, and 0x00000028, respectively. Also, assume that register $s6 contains the value 0x00000100, and that memory contains the following values: Address Value 0x00000100 0x00000064 0x00000104 0x000000c8 0x00000108 0x0000012c Find the value of $s0 at the end of the assembly code. 2.6.6 [10] <2.3, 2.5> For each MIPS instruction, show the value of the opcode (OP), source register (RS), and target register (RT) fields. For the I-type instructions, show the value of the immediate field, and for the R-type instructions, show the value of the destination register (RD) field.

2.3.4 a. f = h - g b. f = g - f - 1 2.3.5 a. 1 b. 0

The following problems deal with translating from MIPS to C. Assume that the variables g, h, i, and j are given and could be considered 32-bit integers as declared in a C program. a. addi f, f, -4 b. add i, g, h add f, i, f 2.3.4 [5] <2.2> For the MIPS statements above, what is a corresponding C statement? 2.3.5 [5] <2.2> If the variables f, g, h, and i have values 1, 2, 3, and 4, respectively, what is the end value of f?

2.1.4. a. f = g + h b. f = g + h 2.1.5. a. 5 b. 5

The following problems deal with translating from MIPS to C. Assume that the variables g, h, i, and j are given and could be considered 32-bit integers as declared in a C program. a. addi f, f, 4 b. add f, g, h add f, i, f 2.1.4 For the MIPS assembly instructions above, what is a corresponding C statement? 2.1.5 If the variables f, g, h, and i have values 1, 2, 3, and 4, respectively, what is the end value of f?

2.2.4 a. f += h; b. f = 1 - f; 2.2.5 a. 4 b. 0

The following problems deal with translating from MIPS to C. For the following exercise, assume that the variables g, h, i, and j are given and could be considered 32-bit integers as declared in a C program. a. addi f, f, 4 b. add f, g, h sub f, i, f 2.2.4 [5] <2.2> For the MIPS assembly instructions above, what is a corresponding C statement? 2.2.5 [5] <2.2> If the variables f, g, h, and i have values 1, 2, 3, and 4, respectively, what is the end value of f?

2.5.4 a. 305419896 b. 319907022 2.5.5 a. Little-Endian Big-Endian Address Data Address Data 12 12 12 78 8 34 8 56 4 56 4 34 0 78 0 12 b. Address Data Address Data 12 be 12 0d 8 ad 8 f0 4 f0 4 ad 0 0d 0 be

The following problems explore the translation of hexadecimal numbers to other number formats. a. 0xabcdef12 b. 0x10203040 2.5.4 [5] <2.3> Translate the hexadecimal numbers above into decimal. 2.5.5 [5] <2.3> Show how the data in the table would be arranged in memory of a little-endian and a big-endian machine. Assume the data is stored starting at address 0.

2.3.1 a. add f, f, g add f, f, h add f, f, i add f, f, j addi f, f, 2 b. addi f, f, 5 sub f, g, f 2.3.2 a. 5 b. 2 2.3.3 a. 17 b. -4

The following problems explore translating from C to MIPS. Assume that the variables f and g are given and could be considered 32-bit integers as declared in a C program. a. f = -g - f; b. f = g + (-f - 5); 2.3.1 [5] <2.2> For the C statements above, what is the corresponding MIPS assembly code? Use a minimal number of MIPS assembly instructions. 2.3.2 [5] <2.2> For the C statements above, how many MIPS assembly instructions are needed to perform the C statement? 2.3.3 [5] <2.2> If the variables f, g, h, i, and j have values 1, 2, 3, 4, and 5, respectively, what is the end value of f?

2.1.1. a. add f, g, h add f, f, i add f, f, j b. addi f, h, 5 addi f, f, g 2.1.2. a. 3 b. 2 2.1.3. a. 14 b. 10

The following problems explore translating from C to MIPS. Assume that the variables f, g, h, and i are given and could be considered 32-bit integers as declared in a C program. a. f = g - h; b. f = g + (h - 5); 2.1.1 For the C statements above, what is the corresponding MIPS assembly code? Use a minimal number of MIPS assembly instructions. 2.1.2 For the C statements above, how many MIPS assembly instructions are needed to perform the C statement? 2.1.3 If the variables f, g, h, and i have values 1, 2, 3, and 4, respectively, what is the end value of f?

1.7.1 Geometric mean clock rate ratio= (1.28 x 1.56 x 2.64 x 3.03 x 10.00 x 1.80 x 0.74) 117 = 2.15 Geometric mean power ratio= (1.24 x 1.20 x 2.06 x 2.88 x 2.59 x 1.37 x 0.92) 117 = 1.62 1.7.2 Largest clock rate ratio = 2000 MHz/200 MHz = 10 (Pentium Pro to Pentium 4 Willamette) Largest power ratio= 29.1 W/10.1 W = 2.88 (Pentium to Pentium Pro) 1.7.3 Clock rate: 2.667 x 10^9/12.5 x 10^6 = 212.8 Power: 95 W/3.3 W = 28.78

The following table shows the increase in clock rate and power of eight generations of Intel processors over 28 years. Processor Clock Rate Power 80286 (1982) 12.5 MHz 3.3 W 80386 (1985) 16 MHz 4.1 W 80486 (1989) 25 MHz 4.9 W Pentium (1993) 66 MHz 10.1 W Pentium Pro (1997) 200 MHz 29.1 W Pentium 4 Willamette (2001) 2 GHz 75.3 W Pentium 4 Prescott (2004) 3.6 GHz 103 W Core 2 Ketsfield (2007) 2.667 GHz 95 W 1.7.1 What is the geometric mean of the ratios between consecutive generations for both clock rate and power? (The geometric mean is described in Section 1.7.) 1.7.2 What is the largest relative change in clock rate and power between generations? 1.7.3 How much larger is the clock rate and power of the last generation with respect to the first generation?

datacenters

Thousands of processors forming a large cluster