Computer Architecture Chapter 8

What is Instruction Level Parallelism?

Provides an environment where more than one instruction can be completed in one clock cycle. (Add more executing units)

What is register renaming?

Refers to the technique used to avoid unnecessary serialization of program operations imposed by the reuse of registers bu those operations. Used to enable out-of-order execution.

What are structural hazards?

Resource Dependencies. Refers to the situation where an instruction requires a hardware resource currently used by another instruction before it can execute. Commonly occurs when instructions are competing for registers.

What are the 4 types of computer achetectures (Flynn)

SISD SIMD MISD MIMD

What is SIMD?

Single Instruction, Multiple Data. Vectored Data. IA-32, MMX. VECTOR PROCESSOR

What is SISD?

Single instruction stream, single data stream. 1 to 1 relationship between the instruction operating and the data its operating on. Von Neuman machine. SCALAR PROCESSOR

What are branch hazards?

Speculative Processing. The path of execution depends on the outcome of an operation.

What are the 2 types of Scheduling?

Static Scheduling Dynamic Scheduling

What is branch prediction?

Used to avoid stalling for control dependencies to be resolved. Used with speculative execution.

What is VLIW?

Very Long Instruction Word. fall under the Static category, compiler does all the work.

What is Write Through?

When information is written to all levels of the cache

What are the two techniques for writing data to the cache?

Write Through Write Back

What is a Data Hazard?

A particular instruction cannot be executed until a preceding instruction has been executed. These can be addressed as follows Read after Write (RAW) Write after Read (WAR) Write after Write (WAW)

What is Speculative execution?

Allows the execution of complete instructions or parts of instruction before being certain whether this execution should take place. Eg. Control Flow speculation. Instructions past a control flow instruction (branch) executed before the target of the control flow instruction is determined.

What is the difference between a cache and a buffer?

Cache -reading -html -cookies -png? Buffer -write

What is piplined cycle time?

CycleTime(unpipelined) / number_of_PipelineStages + Latch Latency

What are 4 classifications of Hazzards?

Data Hazzards (Data Dependencies) Structural Hazards (Resources) Branching Hazards (Speculative Processing) Consistency Issues

What is Write Back?

Data is written to the next level of memory when it is evicted from a level of cache

What is Superscalar Achitecture

Dynamic category, special hardware on the processor does all the work

What is EPIC?

Explicity Parallel Instruction Computing. This is a hybrid of Superscalar and VLIW.

What are the two important streams used in a processor program?

Instruction Stream Data Stream

What is out of order execution?

Makes use of instruction cycles that would otherwise be wasted by a certain type of delay. Executes instructions in an order governed by the availability of input data. Introduces some problems...

What is MIMD?

Multiple Instruction Multiple Data. Machines that include several processors.

What is MISD?

Multiple Instruction, Single Data. Haven't been successfully implemented

What are some ways to optimize your program?

Optimize algorithms Hardware optimization

What are 3 consistency issues?

Processor Consistency Memory Consistency Exception Consistency