computer design

GCC directive, ___________________ must be used to allocate 4 bytes for a variable.

.Word

What is the content of R1 after the following instructions are executed?MOV R1, #0x0F0ADD R1, R1, #0x0F

0XFF

Suppose r0 = 0x20000000 and the following memory layout; what is the value of r1 after running LDRH r1, [r0]?

0x0000A578

Suppose r0 = 0x20000000 and the following memory layout; what is the value of r1 after running LDR r1, [r0]?Memory Address Memory Content 0x20000003 0x12 0x20000002 0x34 0x20000001 0XA5 0x20000000 0x78

0x1234A578

If variable Z is allocated space in memory with address 0x20000000 and Z = 0x128A7502; what is in r0 after the following instruction is executed: LDR r0, =Z

0x20000000

What is the maximum byte addressable memory capacity (in bytes), if the address bus is 11 bits? ( remember that 210 = 1024 = 1 K)

2 KBytes

What is the average memory access time with L1 that has miss rate of 10% and L2 that has miss rate of 2%? The access time for L1 is 2ns, for L2 is 12 ns for main memory is 150 ns.

3.5 ns

The average voltage for a PWM digital waveform with a duty cycle of 75% and a peak value of 5 V is ___________________ .

3.75 V

Suppose we have the instruction "Load 600", what value will be loaded in the accumulator, if the immediate addressing mode is used.

600

What is in eax after this x86 assembly program is executed?PUSH 5PUSH 3PUSH 8POP eax

8

The cache hit rate to execute a given code is 92%, what is the miss rate?

8%

___________________ is the part of CPU that performs all the arithmetic and logic operations.

ALU

For ___________________ architecture only Load and Store instructions can reference the memory.

ARM

Which of the following is a single core processor with no co-processor option?

ARM Cortex-M3

Name a technique that can be used by the processor to determine which device issued the interrupt, when a device interrupt occurs.

All of these answers

A(n) ___________________ is used to convert the assembly program to machine language.

Assembler

Suppose a computer using direct mapped cache has 224 bytes of byte-addressable main memory, and a cache of 128 blocks, where each cache block contains 8 bytes. For four-way set associative cache, to which block of cache the address 0x1895BA maps?

Block 23

C language can be preferred over Python for embedded device software development because:

Both b and c.

__________ consists of a series of conductive paths for transfer of data between components inside a computer.

Bus

The code written in what type of programming language is extremely portable between incompatible computers.

Bytecode interpreted

For this I/O architecture, I/O instructions are executed by a special-purpose processor in the I/O channel itself.

Channel I/O

In today's computers the __________ incorporates the I/O module.

Chipset

Which ARM family is used for real-time applications?

Cortex-R

Which of the following is suitable for processing the I/O of a CD?

DMA

When large volumes of data are to be moved from I/O devices to main memory, which of the following I/O operation techniques is preferred?

Direct memory access(DMA)

A hit ratio of 100% can be achieved if the cache size is increased.

False

DMA operation requires the execution of an ISR by the CPU.

False

GPIO pins can be only used as input or output pins.

False

In general a computer with two levels of cache is expected to have higher miss rate than the computer with one level of cache.

False

The object file generated by the compiler, is an executable file.

False

Upon the receipt of an interrupt, the processor stops executing the current instruction.

False

Which compiler toolset is preinstalled in Raspbian operating system?

GCC

ARM processors have ___________________ architecture.

Harvard

x86 processors have ___________________ architecture.

Harvard?

__________ peripheral devices are suitable for communicating with the computer user.

Human readable

The major functions of __________ include: processor communication, control and timing, device communication, data buffering, and error detection.

I/O module

__________ contains the address on Interrupt Service Routine(ISR).

Interrupt vector

__________ are events that alter the normal flow of execution in a computer system. They are used for I/O, error handling, and other miscellaneous events.

Interrupts

When DMA module takes control of a bus, and while it retains control of the bus, what does the processor do?

It pauses using the bus

Which type of code can run inside web browsers?

Java

In a RISC processor, only ___________________ and ___________________ instructions can access the memory.

LOAD/STORE

Assembly language is considered to be a ___________________ language.

Low level

With a __________ processor, a different thread can be used to execute the ISR, as a result the main program will not be put on hold.

Multicore

Suppose a computer using direct mapped cache has 224 bytes of byte-addressable main memory, and a cache of 128 blocks, where each cache block contains 8 bytes. For fully associative cache, to which block of cache the address 0x189B5A maps?

Not enough information

What is the size of each memory location for ARM processor based systems? (Each memory location has a unique address)

One byte

The ___________________ is responsible for managing computer resources.

Operating system

Which of the following is not a major structural components of the Computer?

Operating system

Point-to-point interconnection and multilane distribution are used for __________.

PCIe

A section of ___________________ is used as stack.

RAM

When the Raspberry Pi is up and running, the operating system is loaded into ___________________ .

RAM

What type of memory cells are used to build cache?

SRAM

For a __________ port, there is only one line used to transmit data, and bits must be transmitted one at a time.

Serial

When a single core processor receives an interrupt; its registers (state) are pushed into __________.

Stack

What is ROM used for, in a computer?

Storing system BIOS and calibration tables

It includes the processor, peripherals, and I/Os on the same chip.

System on a chip

Suppose a computer using direct mapped cache has 224 bytes of byte-addressable main memory, and a cache of 128 blocks, where each cache block contains 8 bytes. How is the address divided into tag, block number and byte number for direct mapped cache?

Tag = 14 bits, block = 7 , byte offset = 3 bits

Suppose a computer using direct mapped cache has 224 bytes of byte-addressable main memory, and a cache of 128 blocks, where each cache block contains 8 bytes. How is the address divided into tag, line number and byte number for four-way set associative cache?

Tag = 16 bits, set = 5 , byte offset = 3 bits

Suppose a computer using direct mapped cache has 224 bytes of byte-addressable main memory, and a cache of 128 blocks, where each cache block contains 8 bytes. How is the address divided into tag, block number and byte number for fully-associative cache?

Tag = 21 bits, block = 3 , byte offset = 0 bits

What happens if two interrupts from two different devices are sent to a single core processor at the same time?

The one with higher priority will be executed first

___________________ are a mix of 16 bit and 32 bit instructions.

Thumb-2

EEPROM is non-volatile.

True

L2 cache can be on the mother board.

True

Register references are faster than cache memory references.

True

Assume FIFO replacement policy is used and all the variables in the program below map to set 1 in a two-way set associative cache. What would be in set 1 upon the complete execution of the program?

Var2 and var3

When a pull-down resistor is used with an input pin, the pin reads a ----------, when the switch is open.

Zero

Which of the following is not an ARM GNU assembler directive?

add

The __________ is used to designate the source or destination of the data on the data bus.

address bus

The intermediate code that is generated in compiling process is typically in ___________________ language?

assembly

Suppose a computer using direct mapped cache has 224 bytes of byte-addressable main memory, and a cache of 128 blocks, where each cache block contains 8 bytes. For direct mapped cache, to which block of cache the address 0x189A5B maps?

block 75

To benefit from spatial locality increase cache ----------------.

block size

Which of the followings is used, for memory allocation of program data in the RAM of Raspberry Pi?

data

The von Neumann architecture is based on which concept?

data and instructions are stored in a single read-write memory the contents of this memory are addressable by location execution occurs in a sequential fashion Correct! all of these answers

Cache is non-volatile.

false

DMA controller deteriorates a computer performance because it allows for direct transfer of data from I/O devices to memory.

false

Part of __________ is allocated for virtual memory.

hard drive

Memory ---------- is adopted in computers to accommodate both high memory capacity and high memory performance

hierarchy

Addressing modes specify where an ___________________ is located.

operand

A ___________________ is used to temporarily store data and then shift it.

register

Native code cache used to store blocks generated by just-in-time compiler are_______________________.

software managed cache

Which architecture does ARM-A72 processor belong to?

v8