CPSC 440 Final Exam
Machine Cycle
-Amount of cycles needed to do either a fetch, read, or write operation -May be more than a single bus cycle -e.g. on an intel 8080 machine, the data width is 8 bits --if the CPU needs to fetch or write 16 bits of data, that will require 2 bus cycles
Electrically Erasable Programmable Read-Only Memory (EEPROM)
-Can be written into at any time without erasing prior contents -Combines the advantage of non-volatility with the flexibility of being updatable in place -More expensive than EPROM
Interleaved Memory
-Composed of a collection of DRAM chips -Grouped together to form an interleaved memory -A word is spread over (interleaved) several memory banks -Typical organization of an interleaved memory with 2^k DRAM banks shown above
read-only memory (ROM)
-Contains a permanent pattern of data that cannot be changed or added to -No power source is required to maintain the bit values in memory -Data of program is permanently in main memory and never needs to be loaded from a secondary storage device -Data is actually wired into the chip as part of the fabrication process
ROM Disadvantages
-Data is wired into the chip as part of the fabrication process -No room for error; if one bit is wrong, the whole batch of ROMs must be thrown out -Data insertion step includes a relatively large fixed cost
Static RAM (SRAM)
-Digital device that uses the same logic elements used in the processor -Binary values are stored using traditional flip flop logic gate configurations -Will hold its data as long as power is supplied to it
Erasable Programmable Read-Only Memory (EPROM)
-Erasure process can be performed repeatedly -Erased by exposure to ultraviolet light then rewritten via an EPROM programmer -More expensive than PROM but it has the advantage of the multiple update capability
Flash Memory
-Intermediate between EPROM and EEPROM in both cost and functionality -Uses an electrical erasing technology, does not provide byte-level erasure -Microchip is organized so that a section of memory cells are erased in a single action or "flash"
Programmable ROM (PROM)
-Less expensive alternative -Nonvolatile and may be written into only once -Writing process is performed electrically and may be performed by supplier or customer at a time later than the original chip fabrication -Special equipment is required for the writing process -Provides flexibility and convenience -Attractive for high volume production runs
Dynamic RAM (DRAM)
-Made with cells that store data as charge on capacitors -Presence or absence of charge in a capacitor is interpreted as a binary 1 or 0 -Requires periodic charge refreshing to maintain data storage -The term dynamic refers to tendency of the stored charge to leak away, even with power continuously applied
SRAM Structure
-Transistors (T1, T2, T3, T4) are cross connected in an arrangement that produces a stable logic state -Logic State 1 (B = 1): C1 is high and C2 is low; T1 and T4 are off, and T2 and T3 are on -Logic State 0 (B = 0): C1 is low and C2 is high; T1 and T4 are on, T2 and T3 are off
Signed-Magnitude Representation Drawbacks
1. Arithmetic operations require both the sign bit and magnitude 2. Two representations of zero +0_10 = 0000 0000 -0_10 = 1000 0000 Therefore, 2's comp is usually used
Evolution of the I/O Function
1. The CPU directly controls a peripheral device 2. A controller or I/O module is added -the CPU uses programmed I/O without interrupts 3. Same configuration as in step 2 is used, but now interrupts are employed -CPU doesn't spend time waiting for an I/O operation to be performed -Increased efficiency 4. The I/O module is given direct access to memory via DMA -It can now move a block of data to/from memory without involving the CPU --Except at the beginning and end of the transfer 5. The I/O module is enhanced to become a processor in its own right, with a specialized instruction set tailored for I/O 6. The I/O module has a local memory of its own and is, in fact, a computer in its own right -With this architecture, a large set of I/O devices can be controlled with minimal CPU involvement
4 Phases of floating point addition/subtraction
1. checks for zeros 2. align the significands 3. add or subtract the significands 4. normalize results
Floating-Point Multiplication
1. if X or Y = 0 then Z = 0 2. Add the exponents 3. Remove bias -if not performed, bias doubled 4. If exponent under/over flows -can be for sign-mag or 2's comp representations -results in double the length, extra bits rounded off 6. Normalize and round -normalization could result in underflow
I/O Module
2 Major Functions -Interface to CPU and memory via system bus or central switch -Interface to one or more peripheral devices by tailored data links
Precision Considerations
23-bit significand the smaller number (y) must be shifted to the right 1 bit to align. During this process, y loses a bit if no guard bits Guard bits are extra bits used to pad the right end of significand
Calculate Operands
Calculate the effective address of each source operand
Single-bus integrated DMA-I/O
Controller may support one or more devices Each transfer uses bus once DMA to memory CPU is suspended once
Bus Cycle
Cycles required to make a single read or write transaction between the CPU and the external memory
Decode Instruction
Determine the opcode and the operand specifiers
I/O Bus
Easily expandable Each transfer uses bus once -DMA to memory CPU is suspended once
Address Recognition
I/O module must recognize one unique address for each peripheral it controls Similar to how each word of memory has an address
Processor Communication
Illustrates that the I/O module must communicate with the CPU and with the external devices
External Device Block: Status Signals
Indicates the state of the device e.g., READY/NOT-READY
Intel 8237A DMA Controller
Interfaces to the Intel 8086 family CPUs and DRAM to provide DMA capability If DMA module needs the system buses -it will send a HOLD signal, HRQ to CPU -CPU will acknowledge by sending HLDA indicating buses are available
IEEE Standard 754
Most important floating-point representation is defined. Standard was developed to facilitate the portability from one processor to another and to encourage the development of sophisticated, numerically oriented programs. Standard has been widely adopted and is used on virtually all contemporary processors and arithmetic coprocessors. IEEE 754-2008 covers both binary and decimal floating-point representations
Parallel and Serial I/O
Parallel Interface -Multiple lines connecting the I/O module and the peripheral -Multiple bits are transferred simultaneously Serial Interface -Only one line used to transmit data, and bits must be transmitted one at a time
Arithmetic and Logic Unit (ALU)
Part of the computer that actually performs arithmetic and logical operations on data. All of the other elements of the computer system are there mainly to bring data into the ALU for it to process and then to take the results back out. Based on the use of simple digital logic devices that can store binary digits and perform simple boolean logic operations.
External Device Block: Data
Set of bits sent-to/received-from the I/O module
Signed-Magnitude Representation
Several ways to represent negative numbers: -All use MSB to represent sign --0 = Positive --1 = Negative Simplest Representation: -Sign bit and sign magnitude +18 = 0001 0010 -18 = 1001 0010 (sign magnitude)
Phase 4: Normalization
Shift significand left and decrement exponent until most significant digit is nonzero -could cause underflow, report underflow and halt Rounding discussed later
Subtraction
Subtraction Rule: To subtract one number (subtrahend) from another (minuend), take the 2's complement (negation) of the subtrahend and add it to the minuend
Machine Readable
Suitable for communicating with equipment Magnetic disk and tape systems, sensors and actuators
Communication
Suitable for communicating with remote devices Terminal, a machine readable device, or another computer
Human Readable
Suitable for communicating with the computer user Video display terminals (VDTs), Printers
Floating-Point Arithmetic
+- 1.S X B^(+-E) -S: Significand -E: Exponent -B: Base Exponent Overflow -A positive exponent exceeds the maximum possible exponent value -In some systems, this may be designated as +-infiniti Exponent Underflow -A negative exponent is less than the minimum possible exponent value -This means that the number is too small to be represented, and it may be reported as 0 Significand Underflow -In the process of aligning significands, digits may flow off the right end of the significand -Some form of rounding is required Significand Overflow -The addition of two significands of the same sign may result in a carry out of the most significant bit -This can be fixed by realignment.
Typical 32-Bit Floating-Point Format
+- 1.S X B^(+-E) S - Significand E - Exponent B - Based
Resource Hazards
A resource hazard occurs when two or more instructions that are already in the pipeline need the same resource. The result is that the instructions must be executed in serial rather than parallel for a portion of the pipeline. A resource hazard is sometimes referred to as a structural hazard.
Unsigned Representation
All numbers are positive. For unsigned numbers, all the bits in the number represent the magnitude of that number.
Read After Write
An instruction modifies a register or memory location Succeeding instruction reads data in memory or register location Hazard occurs if the read takes place before write operation is complete
Write After Read
An instruction reads a register or memory location Succeeding instruction writes to the location Hazard occurs if the write operation completes before the read operation takes place
Predict-Taken Strategy
Assumes branch will always be taken Instruction Fetch Stage: always fetches from the branch target. If not branching: Logic in CPU will detect this and will instruct CPU to a. Fetch the next sequential instruction b. Flush the pipeline
Predict-Never-Taken Strategy
Assumes branch will not be taken Most popular approach Instruction Fetch Stage: always fetches the next sequential address. If branch: Logic in CPU will detect this and will instruct CPU to a. fetch the next instruction from target address b. flush the pipeline
Internal Reference Alphabet (IRA)
Basic unit of exchange is the character -Associated with each character is a code -Each character in this code is represented by a unique 7-bit binary code; 128 different characters can be represented -Example: 'K' = 1001011 Characters are of two types: 1. printable: alphabetic, numeric, and special characters that can be printed on paper or displayed on a screen 2. control: have to do with controlling the printing or displaying of characters. Example is a carriage return (CR). Other control characters are concerned with communications procedures.
Drawbacks of programmed and interrupt driven I/O
Both forms of I/O suffer from two inherent drawbacks: 1. I/O transfer rate limited by the speed with which the CPU can test/service a device 2. The CPU is tied up in managing and I/O transfer When large volumes of data are to be moved, a more efficient technique is DMA
SRAM versus DRAM
Both volatile: power must be continuously supplied to the memory to preserve the bit values Dynamic cell: -simpler to build, smaller -more dense (smaller cells=more cells per unit area) -less expensive -requires the supporting refresh circuitry -tend to be favored for large memory requirements -used for main memory Static Cell: faster, used for cache memory (both on and off chip)
Interrupt Driven I/O
CPU issues and I/O command, continues to execute other instructions, and is interrupted by the I/O module when the job is done
Floating-Point Representation
Can approximate a wider range of nubers The numbers are, in general, represented approximately to a fixed number of significant digits (i.e. significand or mantissa) and scaled using an exponent
Typical DMA Module
Capable of mimicking CPU and can take over control of the system. -Must use bus when CPU isn't using it -Or force the CPU to suspend operation temporarily (cycle stealing) CPU sends command to DMA module -read/write request (control line) -I/O device addresses (data lines) -Memory address to read/write (address lines) -# of words to read/write (data lines/data count/data register) CPU continues work, DMA reads data from/writes to memory directly -when done, DMA interrupts CPU
External Device Block: Control Logic
Controls the device's operation in response to direction from the I/O module
External Device Block: Transducer
Converts data into appropriate forms of energy needed for I/O e.g., electrical signal to magnetic field and vice-versa
Control and Timing Requirement
Coordinate flow of traffic between internal resources and external devices
DMA Operation
Cycle Stealing: -CPU suspended just before DMA module needs to use the bus -DMA controller takes over bus for a cycle It transfers one word and returns control of CPU Not an interrupt -CPU doesn't save context -CPU can do something else Causes the CPU to execute more slowly Still far more efficient than interrupt-driven or programmed I/O
Layout of Data Bits and Check Bits
Syndrome Word -Result from the comparison -If all 0's, no error -If only one 1, error occurred in the corresponding check bit -If more than one 1's, syndrome indicates position of data bit error
Command Decoding
The I/O module accepts commands from the CPU (signals on the control bus)
Direct Memory Access (DMA)
The I/O module and main memory exchange data directly without CPU involvement
Write After Write
Two instructions both write to the same location Hazard occurs if the write operations take place in the reverse order of the intended sequence
read
causes the I/O module to obtain an item of data from the peripheral and place it in an internal buffer
write
causes the I/O module to take an item of data from the data bus and subsequently transmit that data item to the peripheral
Phase 2: Significand Alignment
significands need to be aligned before the operation if the exponents are not equal repeat the following on the smaller number until exponents match or a zero significand results 1. increment exponents 2. shift significand to the right once 3. if a zero significand, then report other number as result
Floating-Point Addition and Subtraction
Floating point addition/subtraction more complex than floating point mult/division, because of need for alignment
Error Correction
Hard Failure: -Permanent physical defect -Memory cell or cells affected cannot reliably store data but become stuck at 0 or 1 or switch erratically between 0 and 1 -Can be caused by: harsh environmental abuse, manufacturing defects, wear Soft Error: -Random, non-destructive event that alters the contents of one or more memory cells -No permanent damage to memory -Can be caused by: power supply problems, alpha particles
Branch Prediction - Taken/Not Taken Switch
History bits used to reflect recent history of the conditional branches. These bits are used by CPU to make a decision on the next conditional branch. Kept in temporary high speed storage separate from main memory. Drawback: if the decision is made to take the branch, the target instruction cannot be fetched until target address is decoded.
Parity Bit
IRA-encoded characters are almost always stored and transmitted using 8 bits per character The 8th bit is a parity bit used for error detection The parity bit is the most significant bit and is therefore labeled b_8 The bit is set such that the total number of binary 1's in each octet is always odd (odd parity) or always even (even parity) Thus a transmission error that changes a single bit, or any odd number of bits, can be detected
Integer Representation
In the binary number system, arbitrary numbers can be represented with: -the digits zero and one -the minus sign (for negative numbers) -the period or radix point (for numbers with a fractional component) For purposes of computer storage and processing, we do not have the benefit of special symbols for the minus sign and radix point. Only binary digits may be used to represent numbers.
Keyboard/Monitor
Input (Keyboard) -Pressing a key generates an electronic signal and is sent to the transducer in the keyboard -Signal is translated into IRA code bit pattern -This bit pattern is then transmitted to the I/O module in the computer Output (Monitor) -IRA code characters are transmitted to an external device from the I/O module -Transducer interprets the code -Sends the required electronic signals to the output device -e.g. display the indicated character or perform the requested control function
Loop Buffer Benefits
Instructions fetched in sequence will be available without usual memory access time If a branch occurs to a target just a few locations ahead of the address of the branch instruction, the target will already be in the buffer This strategy is particularly well suited to dealing with loops
I/O Module Interfaces
Interfaces between an I/O module and external devices can be either point-to-point or multiport Point-to-point -Provides a dedicated line between the I/O module and the external device -On small systems (PCs, workstations) typical point-to-point links include those to the keyboard, printer, and external modem Multipoint -Used to connect several external devices together -External interfaces are used to support external mass storage devices (disk and tape drives) and multimedia devices (CD-ROMs, video, audio).
I/O Module
Needed as an interface between peripherals and system bus, because: -Wide variety of peripherals -Mismatch of transfer rates between peripherals and memory/processor -Different data formats and word lengths I/O module has two major functions: 1. Interface to CPU and memory via system bus or central switch 2. Interface to one or more peripheral devices by tailored data links
Density of Floating-Point Numbers
Numbers represented in floating-point notation are not spaced evenly along the number line. Values get closer together near the origin and farther apart as you move away. Math Trade-Off: -May produce results that are not exact -Needs to be rounded to the nearest value that the notation can represent.
Control Hazard
Occurs when the pipeline makes the wrong decision on a branch prediction Brings instructions into the pipeline that must subsequently be discarded
Device Communication
On the other side, the I/O module must be able to communicate with the devices. Involved commands, status info, and data
Addition
Overflow Rule: if two numbers are added, and they are both positive or both negative, then overflow occurs if and only if the result has the opposite sign.
Execute Instruction
Perform the indicated operation and store the result, if any, in the specified destination operand location
Status Reporting
Peripherals are usually slow. Need to know the status of the I/O module. Common status signals are BUSY and READY
Fixed-Point Representation
Possible to represent a range of positive and negative integers on or near 0 By assuming a fixed binary (radix) point, this format allows the representation of numbers with a fractional component as well. Limitations: Very large numbers cannot be represented nor can very small fractions; the fractional part of the quotient in a division of two large numbers could be lost
I/O Operation Techniques
Programmed I/O Interrupt Driven I/O Direct Memory Access (DMA)
External Devices
Provide a means of exchanging data between external environment and computer Attach to the computer by a link to an I/O module -The link is used to exchange control, status, and data between the I/O module and the external device
RAM
RAM Technology is divided into two technologies: Dynamic RAM and Static RAM
2's Complement Representation
Range: -2^(n-1) to 2^(n-1) - 1 # of Representations of Zeros: one Negation: Take the boolean complement of each bit of the corresponding positive number, then add 1 to the resulting bit pattern viewed as an unsigned integer. Expansion of Bit Length: Add additional bit position to the left and fill in with the value of the original sign bit. Subtraction Rule: to subtract B from A, take the 2's complement of B and add it to A. Examples in slides 7 through 12
Fetch Instruction
Read the next expected instruction into a buffer
Floating-Point Division
Same process as multiplication except... if Y = 0 then Z = infinity exponents subtracted
Branch History Table
Saves more info about target instruction Allow instruction to be fetched as soon as branch decision is made Table is treated as a small cache Each entry in the table has 3 elements 1. address of the branch instruction 2. target address information 3. history bits that record the state of use
I/O Channel Arhcitecture
Selector Channel -Controls multiple high-speed devices -At any one time, it's dedicated to the transfer of data with one of those devices Multiplexor Channel -Can handle I/O with multiple devices at the same time
Loop Buffer
Small, very high speed memory maintained by the instruction fetch stage of the pipeline and containing the n most recently fetched instructions, in sequence Similar in principle to a cache dedicated to instructions except the loop buffer only retains instructions in sequence and is much smaller in size and cost.
Write Operand
Store the result in memory
Programmed I/O
Data are exchanged between the CPU and the I/O module CPU executes a program that gives it direct control of the I/O operation When the CPU issues a command, it must wait until the I/O operation is complete If the CPU is faster than the I/O module, CPU time wasted
Fly-By DMA Controller
Data doesn't pass through and is not stored in DMA chip -DMA only between I/O port and memory -Not between two I/O ports or two memory locations Can do memory-to-memory via register The Intel 8237A contains four DMA channels -Programmed independently -Any one active -Numbered 0,1,2, and 3
Single Bus, Detached DMA
Data exchanged between memory and I/O module through DMA module using programmed I/O Inexpensive but inefficient -each transfer uses bus twice -I/O to DMA then DMA to memory -CPU is suspended twice
External Device Block: Control Signals
Determine the function that the device will perform Examples: -Send data to the I/O module (INPUT/READ) -Accept data from the I/O module (OUTPUT/WRITE) -Report status, or perform some control function particular to the device (e.g., position a disk head)
Branch History Table Strategy
Each pre-fetch triggers a lookup in the branch history table If no match is found, the next sequential address is used for the fetch If a match is found, a prediction is made based on the state of the instruction: either the next sequential address or the branch target address is fed to the select logic
I/O Module Function Categories
Error Detection Control and Timing Data Buffering Processor Communication Device Communication
Error Detection
Error reporting to the CPU Types of errors: mechanical and electrical malfunctions, transmit error
Intel 8237A DMA Controller Example
Example DMA module is to transfer a block of data from memory to disk 1. Peripheral device (e.g., disk controller) requests DMA by pulling DREQ high 2. DMA pulls HRQ high (hold request to CPU) -DMA must keep this signal high during the entire task 3. CPU finishes present bus cycle and acknowledges (HLDA pulled high by CPU) 4. DMA activates DACK to tell peripheral device to start transfer 5. DMA starts transfer of data from memory to peripheral by putting the address of 1st byte on the address bus and activates MEMR 6. Then the DMA activates IOW to write the peripheral 7. Steps 5 and 6 are repeated until the entire block is transferred 8. After the DMA finishes, it deactivates HRQ and lets the CPU regain control of the buses
Data
Exchanged between the CPU and the I/O module over the data bus
Pipeline Stages
Fetch Instruction (FI) Decode Instruction (DI) Calculate Operands (CO) Fetch Operands (FO) Execute Instructions (EI) Write Operand (WO)
Fetch Operands
Fetch each operand from memory. Operands in registers need not be fetched
I/O module structure
System bus lines: signal lines that connect I/O module to CPU via bus Data registers: used to buffer data transferred to/from the module Status/Control registers: provide current status info to CPU. May also function as a control register I/O Logic module: interacts with CPU via a set of control and address lines Control Lines: used to issue commands to the I/O module from CPU. Some may be used by the I/O module I/O module must also be able to recognize/generate addresses associated with the devices it controls. Finally, the I/O module contains logic specific to the interface with each device that it controls
External Device Block: Buffer
Temporarily holds data being transferred between the I/O module and the external environment A buffer size of 8 to 16 bits is common
I/O Commands
There are 4 types of I/O commands that an I/O module may receive when it is addressed by a CPU: 1. control 2. test 3. read 4. write
Branch Prediction
This algorithm requires two consecutive wrong predictions to change the prediction decision.
Data Buffering
Transfer Rate: Memory/Processor -> high Most peripherals -> much lower Data from main memory to I/O module is sent in rapid burst. It is buffered in I/O module then sent to peripheral at its data rate. Data from I/O to main memory: Data buffered in I/O module then sent to memory at its data rate. This prevents bottleneck of memory during slow transfer operations. Buffer needed if I/O module rate higher than memory I/O module must be able to operate at both device and memory speeds
Biased Representation
Value (bias) subtracted from exponent field to get the true exponent value Typical bias: 2^(k-1) - 1 where k is the number of bits in the biased exponent
Branch Prediction
Various techniques can be used to predict whether a branch will be taken: 1. Predict never taken 2. Predict always taken 3. Predict by opcode These approaches are static. They do not depend on the execution history up to the time of the conditional branch instruction 1. Taken/not taken switch 2. Branch history table These approaches are dynamic. They depend on the execution history.
2's Complement Division
We can use the unsigned binary division To deal with negative numbers, the remainder is defined by D = Q X V + R Where Q is the quotient, V is the divisor and D is the dividend The remainder is the value of R needed for the preceding equation to be valid
Prefetch Branch Target
When a conditional branch is recognized, the target of the branch is pre-fetched in addition to the instruction following the branch Target is then saved until the branch instruction is executed If the branch is taken, the target has already been pre-fetched
Phase 3: Addition
add signed significands -if results in zero, then report Z=0 Operation could result in significand overflow -shift significand right -increment exponent If this results in a exponent overflow, report overflow and halt
Phase 1: Zero Check
if either operand (x or y) = 0, report the other as result
Control
used to activate a peripheral and tell it what to do
test
used to test various status conditions associated with an I/O module and its peripherals
Six State Instruction Pipeline
Logic needed for branch and interrupts Other logic needed to handle memory/register conflicts
Normal Word
MSB of significand !=0 For base 2, MSB of significand = 1
Instruction Cycle
The number of machine cycles needed to complete an instruction
