Digital Systems II Quizzes

A low active 7-segment display turns on a segment when the corresponding input is _____________. The driving circuit is called _______________. 0____________common - cathode 1____________comoon - cathode 0____________common - anode 1____________common - anode

0____________common - anode

A 3:8 decoder has three high-active inputs W0 to W2 and low-active outputs Y0 to Y7 and high-active gate control G1 and low-active gate control G2AN and G2BN.When W0 W1 W2 =1 0 0, and G1 G2AN G2BN = 1 0 0, the output Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7=______________________ 00000000 11111111 11110111 00001000 10111111 01000000

10111111

In Verilog, 4'h10 represents the following decimal number______________ 10 12 14 16

16

After the following Verilog statements wire [0:3] A=4'b0101; wire [0:3] B=8'b1010; wire [0:1] C; assign C={A[1],B[1]}; C[0]=__________, C[1]= _______ 0 ______0 0______1 1______0 1_______1

1______0

If a=1, b=0, Verilog expression {a, b} represent decimal value of 0 1 2 3 10

2

How many 2: 1 multiplexers are needed to implement a 4: 1 multiplexer? 2 3 4 5

3

A 10:1 multiplexer has 10 data inputs and 1 output. How many select line does it have? 2 3 4 5 10

4

Verilog to Quartus II is like ___________ Calculus to MATLAB C++ to Microsoft Visual Studio English to USA K-Map to Boolean Algebra

C++ to Microsoft Visual Studio

To test a design on DE2 board, pin assignment is needed. This can be done with manual pin assignment for each input and output or by importing a pin assignment file. Why is this needed? Without pin assignment, the board hardware resources cannot be used for the test. Without pin assignment, program file (sof) cannot be programmed to the board. Without pin assignment, all inputs will be floating. Without pin assignment, all outputs will be logic high.

Without pin assignment, the board hardware resources cannot be used for the test.

A half-adder can be implemented using one ______ gate and one ___________ gate and xnor and xor nand xnor nand xor

and xor

Find an equivalent Verilog statement for the codes as follows always @(*) if (S==0) F=i0; else F=i1; F=S ? I0 : I1; F=S? I1 : I0; assign F= S ? I0 : I1; assign F= S? I1 : I0;

assign F= S? I1 : I0;

To describe the hardware representing the Product-of-Sum (PoS) expression F=(x1+x2)*((x2+x3), we can use _______ F=(x1+x2)*(x2+x3); assign F=(x1+x2)*(x2+x3); F=(x1|x2)&(x2|x3); assign F=(x1|x2)&(x2|x3); F=(x1|x2)&(x2|x3); assign F=(x1|x2)&(x2|x3);

assign F=(x1|x2)&(x2|x3);

Complete missing statement as in the Verilog design to test 2:1 multiplexer mux2 module testMux2 (SW, LEDG, LEDR); input [2:0] SW; // SW0 as i0, SW1 as i1, SW2 as s output [2:0] LEDR; output [0:0] LEDG; // LEDG0 f ___________________________ // LEDR to reflect SW ___________________________ // an instance for mux2 (s, i0, i1, f) assign LEDR=SW; _______________mux2 u0 ( SW[2], SW[0], SW[1], LEDG); LEDR=SW; ____________________mux2 u0 (SW[0], SW[1], SW[2], LEDG[0]); assign LEDR=SW;_______________ mux2 u0( SW[2], SW[1], SW[0], LEDR[0]); LEDR=SW;_____________________mux2 u0 (SW[2], SW[0], SW[1], LEDG); None of above

assign LEDR=SW; _______________mux2 u0 ( SW[2], SW[0], SW[1], LEDG);

f=x ? y can be represented using Verilog statement ____________ assign f=x + y ; assign f=x | y; assign f=x ^ y; assign f=x ~^ y;

assign f=x ^ y;

To perform 64-bit addition for X[63:0] and Y[63:0] to generate S[63:0] and carry C, we may use___________ assign { C, S}=X + Y; assign {S, C}=X + Y; assign {C, S}=X | Y; assign {S, C}= X | Y;

assign { C, S}=X + Y;

To convert a 4-bit SW input to 7-segment code HEX0 display output, we can instantiate a module bcd2leds(seg7, bin4) which has bin4 as 4-bit input, seg7 as 7-bit output. as___________________ bcd2leds U1 (HEX0, SW); U1 bcd2leds (HEX0, SW); bcd2leds U1 (SW, HEX0); U1 bcd2leds (SW,HEX0);

bcd2leds U1 (HEX0, SW);

In this class, EDA stands for ___________ Electronic Design Automation Economic Development Administration Enterprise Digital Assistant Exploratory Data Analysis

Electronic Design Automation

A full-adder module FA(x,y, cin, s, cout); is available. Below is a half-adder design based on FA. module HA (x, y, s, c); input x, y; output s, c; ______________________// missing statement endmodule The missing statement can be _________ FA u0 ( x, y, c, s, 0); FA u0 ( x, y, 0, c, s); FA u0 (0, x, y, c, s); FA u0( x, 0, y, s, c);

FA u0( x, 0, y, s, c);

A half-adder is given as follows module HA(x, y, c, s); input x, y; output c, s; assign {c, s} = x+y; endmodule To test the HA module on DE2 FPGA board using SW[0] for x, SW[1] for y, LEDG[0] for s, LEDG[1] for c, we can use __________ HA myha (SW[0], SW[1], LEDG[0], LEDG[1]); myfa HA (SW[1], SW[0], LEDG[1], LEDG[0]); HA myha (SW[0], SW[1], LEDG[1], LEDG[0]); myfa HA (SW[1], SW[0], LEDG[0], LEDG[1]);

HA myha (SW[0], SW[1], LEDG[1], LEDG[0]);

What is wrong with the Verilog module below module example (I0, I1, S, F); input I0, I1, S; output reg F; always @(*) case (S) ; 0: F=I0; 1: F=I1; endcase endmodule output reg F; should be output f; case (s) ; should be case (s) F=I0; should be assign F=I0 (same for F=I1) case statements cannot be used here since we only have two cases

case (s) ; should be case (s)

Verilog is __________ case-sensitive case-insensitive

case-sensitive

In Verilog, the keywords case and endcase are used for procedural statements similar to the C/C++ switch-case statements.Which keyword is used to represent all other cases? otherwise other else default

default

A sequential logic circuit must have ________ logic gate(s) such as and, or , not combinational logic building block (s) such as multiplexer, decoder latch (es) flip-flop(s)

flip-flop(s)

The following Verilog statement as follows represents ________ or u0(a,b,c); or gate with three inputs a,b,c or gate with two inputs a,b or gate with two inputs b,c or gate with two inputs a,c

or gate with two inputs b,c

To describe an 3-input OR gate with inputs a, b, c and output f, we can use _______ or3 u0(f, a, b, c); OR3 u0(a, b, c, f); or u0(f, a, b, c); OR u0(a, b, c, f);

or u0(f, a, b, c);

Complete the module for a 2: 1 multiplexer with inputs i0, i1, select s, and output f as follows module mx2 (i0, i1, s, f); input i0, i1, s; _______ f; always @ (*) if (_______) f=i0; else f=i1; endmodule out __________ s output reg_____________ ~s input _______________ s input reg ______________ ~s

output reg_____________ ~s