Digital Test 2

Just like the Analogy: Due to road construction, four lanes (the data inputs) may be reduced to a single lane (the single output). A policeman (the select inputs) selects which one lane currently passes through by blocking the other lanes. Just as sometimes the police have one lane open, but no cars are coming through at that time, when the input for the data input selected =0, the output = __________.

0

To do normal addition on the adder/subtractor, the input sub must equal ____________.

0

Subtract the following 4-bit, fixed-precision, 2s complement numbers and give the 4-bit result along with the overflow result. 0011 - 0001

0010, overflow did not occur

Add the following 8-bit, fixed-precision, 2s complement numbers and give the 8-bit sum along with the overflow result. 0111 1110 + 1011 0101

0011 0011, overflow did not occur

Add the following 4-bit, fixed-precision, 2s complement numbers and give the 4-bit sum along with the overflow result. 0111 + 1101

0100, overflow did not occur

Subtract the following 8-bit, fixed-precision, 2s complement numbers and give the 8-bit result along with the overflow result. 0101 1110 - 1111 0101

0110 1001, overflow did not occur

To do subtraction on the adder/subtractor, the input sub must equal ____________.

1

Add the following 4-bit, fixed-precision, 2s complement numbers and give the 4-bit sum along with the overflow result. 1101 + 1011

1000, overflow did not occur

Add the following 8-bit, fixed-precision, 2s complement numbers and give the 8-bit sum along with the overflow result. 1101 1110 + 1011 0101

1001 0011, overflow did not occur

Add the following 4-bit, fixed-precision, 2s complement numbers and give the 4-bit sum along with the overflow result. 0111 + 0010

1001, overflow occurred

Subtract the following 4-bit, fixed-precision, 2s complement numbers and give the 4-bit result along with the overflow result. 0111 - 1101

1010, overflow occurred

Add the following 4-bit, fixed-precision, 2s complement numbers and give the 4-bit sum along with the overflow result. 0101 + 0110

1011, overflow occurred

Subtract the following 8-bit, fixed-precision, 2s complement numbers and give the 8-bit result along with the overflow result. 0101 1110 - 1000 0101

1101 1001, overflow occurred

Subtract the following 4-bit, fixed-precision, 2s complement numbers and give the 4-bit result along with the overflow result. 0101 - 0110

1111, overflow did not occur

A half Adder creates an arithmetic circuit that adds _________ single bit inputs.

2

A full Adder creates an arithmetic circuit that adds _________ single bit inputs.

3

Because two's-complement representation performs subtraction by complementing and adding, a single adder circuit can perform either addition or subtraction, thus saving circuit size. What device must be placed in the circuit to select between addition or subtraction.

4 2:1 Muxes

A 4-bit subtractor can be made from a 4-bit adder along with 4 inverters into input B[3:0] and setting Cin to 1. This can be written algebraically as

A - B = A + (-B)

Select lines

A mux's control inputs

Overflow

A value that can't be represented in the given number of bits as a result of adding two numbers of the same sign

Write the equation for the output C( or CarryOut) for a half adder, Make a truth table if necessary.

C(A,B) = AB

Write the minimum SOP equation for the output C( or CarryOut) for a full adder. Make a kmap from your truth table.

C(A,B,Cin) = AB + A(Cin) + B(Cin)

Write the SOP CANONICAL equation for the output C( or CarryOut) for a full adder. Hint: Make a truth table if necessary.

C(A,B,Cin) = AB(Cin) + AB(Cin)' + AB'(Cin) + A'B(Cin)

Given the following function, determine the minimum SOP equation. F(A, B, C, D) = m(0, 1, 2, 3, 8, 9, 10, 11)

F(A, B, C, D) = B'

Given the following function, determine the minimum SOP equation. F(A, B, C, D) = m(0, 2, 8, 10)

F(A, B, C, D) = B'D'

Given the following function, determine the minimum SOP equation. F(A, B, C, D) = m(0, 4, 8, 12)

F(A, B, C, D) = C'D'

Given the following function, determine which of the following equations would be minimum SOP equation. Mark all choices that are minimum SOP. F(A, B, C, D) = m(0, 1, 5, 7, 10, 14, 15)

F(A,B,C,D) = A'B'C' + A'BD + ABC + ACD'. F(A,B,C,D) = A'B'C' + A'C'D + BCD + ACD'. F(A,B,C,D) = A'B'C' + A'BD + BCD + ACD'

Given the following function, determine the minimum SOP equation. F(A, B, C, D) = m(0, 1, 2, 3, 4, 6, 8, 9, 10 , 11, 12, 14)

F(A,B,C,D) = B' + D'

critical path

If multiple paths exist from inputs to output, the circuit's delay is the longest path

Number of select inputs a mux needs for N data inputs

Log(2)N

Select which of the following equations implement a 4:1 Multiplexer. HINT: Write the truth table for the select inputs for a 4:1 Mux to determine the circuit implementation.

Out = S1'S0'D0 + S1'S0D1 + S1S0'D2 + S1S0D3

To make a truth table for a mux, we could only write the rows where a specific input is selected, and the other inputs as DON'T CARES. For a 4:1 Multiplexer, for what is the product term associated with D3 where the output OUT = 1.

Out = S1S0D3

Shown is a 4:1 Multiplexer. What values of S1S0 select D1 to pass through to the output.

S1S0 = "01"

ICQ4

Stuff From ICQ4

ICQ6

Stuff From ICQ6

ICQ 7

Stuff From ICQ7

ICQ8

Stuff From ICQ8

ICQ9

Stuff From ICQ9

Zybooks 6

Stuff From Zybooks 6

Zybooks 7

Stuff From Zybooks 7

Zybooks 8

Stuff From Zybooks 8

Write the equation for the output SUM for a half adder. The inputs are named A, B. Make a truth table if necessary.

Sum(A,B) = A'B + AB'

Write the SOP equation for the output SUM for a full adder. Hint: Make a truth table.

Sum(A,B,Cin) = AB(Cin) + A'B'(Cin) + A'B(Cin)' + AB'(Cin)'

Shown is a 4:1 Multiplexer. If the values of S1S0 select D1 to pass through to the output, and D1 = "0", then the output, OUT =

UNKNOWN

Two most common HDLs

Verilog and VHDL

full adder

a circuit that adds three bits and generates a sum and carry-out.

half adder

a circuit that adds two bits and generates a sum and carry-out bit.

expression

a combination of items, like inputs, variables, literals, and operators, that evaluates to a value

encoder

a combinational circuit that converts 1 of N inputs to a binary value using logN outputs

Decoder

a combinational circuit that converts N inputs to a 1 on one of 2^N outputs

Priority encoder

a combinational circuit that outputs the binary value for the highest priority input that is 1, where a higher numbered inputs has higher priority

Multiplexor (Mux)

a combinational circuit that passes one of multiple data inputs through to a single output, selecting which one based on additional control inputs

N-bit shifter

a combinational logic component that can shift an N-bit input by a fixed amount

tradeoff

a design decision that improves one implementation metric while worsening another

Optimization

a design decision that improves some metric(s) without worsening any others

identifier

a designer-defined name used for items such as modules, inputs, and outputs.

implementation metric

a measurement of an implementation's goodness

port

a named input or output of a module.

Shifting

a process used to reposition bits of data, either to the left or to the right

N-bit barrel shifter

a shifter component that can shift data by any number of positions

hardware description language (HDL)

a textual language for describing digital systems, as Boolean functions, gate circuits, or other forms.

keyword

a word that is part of the language, like the words module and input

Configure the adder/subtractor to do the following arithmetic. 5 - 4

a3a2a3a0 = 0101. b3b2b3b0 = 0100. sub = 1

enable input

additional input for decoders that sets all outputs to 0s when it equals 0, and enables the decoder for normal behavior when it equals 1

incrementer

adds 1 to a number

Verilog

an HDL that originated in 1985 at a company called Gateway Design Automation (now Cadence)

VHDL

an HDL that was first published in 1987 as an IEEE standard, developed at the behest of the U.S. Dept. of Defense

complement

another number that yields a sum of 100...00 and can be used to represent the negative of that number.

assignment statement

assigns the left-side variable with the result of the right-side expression

synthesis tool

automatically converts specified behavior into a circuit.

The select line each of the muxes which chooses between B and inverted B is also connected to the ___________ input of the adder.

cin

carry-ripple comparator

compares two N-bit numbers from left to right, with the result of each digit's comparison "rippling" to the next digit

one-bit comparator

compares two bits a and b only if the eq input was 1 from the higher digit, else just passing along a gt 1 or an lt 1

Comparator

compares two numbers, indicating whether the numbers are equal, or which number is greater

adder

computes A + B, where A and B are N-bit numbers

Subtractor

computes A - B, where A and B are N-bit numbers

2X4 Decoder

converts two inputs to a 1 on exactly one of four outputs

module

defines a new component

always procedure

defines a statement sequence that executes throughout simulation

sensitivity list

defines the inputs and variables whose value changes cause the procedure to execute

simulation

determines what output values a digital system would generate over time.

A 4-bit adder can be made from four full adder circuits by cascading them together. The carryout of each full adder becomes the carry in of the next adder. To use four full adders, the least significant adder must have cin tied to _________.

ground (0)

4x1 mux

has 4 data inputs, 1 data output, and requires 2 select inputs

A four bit incrementer can be built from four half adders by cascading them together. The carryout of each half adder becomes the b input of the next adder. To use four half adders as a 4-bit incrementer, the least significant half adder must have input b tied to _______________.

high (1)

For a subtractor built from an adder, the adder is configured to subtract by setting the adder's cin bit to ___

high (1)

A half adder can be used as a(n) ________________ circuit, which adds 1 to a number.

incrementer

two's complement representation

inverts every bit and adds 1

Signed numbers

involve both positive and negative numbers, like 3 and -3

Unsigned numbers

involve only non-negative numbers, like 0 and 3

carry-ripple adder

mimics adding by hand, adding a digit's pair of bits and carry-in bit, and generating a sum and carry-out bit

N-bit multiplier

multiplies two N-bit numbers to yield a 2N-bit product

4X2 Encoder

outputs a binary value on the two output lines indicating which of the four inputs was 1

Bitwise operators

perform the specified Boolean operation on each bit of the operands.

gate delay

quick approach for approximating circuit delay counts the number of gates from a circuit's inputs to output

A multiplexor is a combinational circuit that passes one of multiple data inputs through to a single output. Additional inputs are the controls that determine which input is selected. The control inputs are called______________ inputs.

select

variable

stores a value, with the value being updated by assignment statements, and is declared using the reg keyword

carry-lookahead adder

uses logic to quickly pre-compute the carry for each digit, and thus has less delay than a carry-ripple adder, but larger size, representing a tradeoff.

signed-magnitude representation

uses the left bit for the sign: 0 means positive, 1 means negative.

the digit generates a carry-out of 1 regardless of the carry-in

when a and b are both 1s

the digit propagating the carry-in to carry-out

when a or b is one