ELEC 274 Question Database
There are variants of Jump and Call instructions which can use full 32 addresses by using a processor register.
True
To ensure that same data is not read more than once, KIN flag of the keyboard status register is cleared to 0 after reading data from keyboard interface
True
To exploit spatial locality, a cache block with multiple adjacent words is transferred to cache from memory.
True
To exploit temporal locality, information is brought into cache on its first use.
True
Vectored interrupts reduce service latency as no instructions are executed to poll many devices
True
Virtual memory provides larger apparent size of memory by transparently using secondary storage
True
When Memory Function Complete (MFC) signal is asserted, the processor proceeds to the next stage in its execution sequence.
True
When data is not in cache, several clock cycles are needed for the memory access stage.
True
A virtual memory hit is called a page fault.
True Correct Answer False
The following value 0x11223344 is stored in a 32-bit word at address 0x2000. If the computer is little-endian, the contents of the byte at 0x2003 is:
0x33 0x44 0x22 Correct Answer 0x11
In a world aligned byte addressable memory with 2 bytes per word, the words addresses are:
1, 2, 3, ... Correct Answer 0, 2, 4, ... 0, 4, 8, ... 0, 8, 16, ...
A common practice is to use stack that grows in the direction of
arbitrary memory addresses Correct Answer decreasing memory addresses increasing memory addresses both sides of memory addresses
For a specific stack frame, the contents of frame pointer (FP)
are non-volatile always contain 32-bit zero value Correct Answer remain fixed keep changing
Which of the following coordinates the operation of computer operations:
arithmetic and logic unit (ALU) Input/output units main memory Correct Answer control unit
Which of the following is NOT part of the processor?
arithmetic and logic unit (ALU) Correct Answer complete stack input/output devices registers
Which of the following is not NOT one of the five functional units of a computer:
arithmetic and logic unit (ALU) Correct Answer operating system input device memory unit
Index addressing mode (displacement mode) provides the address
as an immediate value Correct Answer in a register with an offset value from the origin of program data in a processor register
During the execution of an instruction In a five-step datapath, the following steps need to wait for Memory Function Completed (MFC):
During Step 1, and during step 4 if the instruction is a LOAD or STORE instruction.
Field Programmable Gate Array (FPGA) is an example of
EEPROM
Which of the following is NOT performed by the processor control signals?
Enabling of inter-stage registers
In a cache using direct mapping, the high-order 8 bits of the address (for shown address partitioning) are compared with the block bits associated with that cache location.
False
In a processor with 32-bit word using byte-addressable memory, the low-order (right most) 2 bits of the address determine which word will be accessed.
False
In interrupts method of exchanging information between the processor and I/O device, interrupt-request signal is initiated by the processor
False
In memory chips, a cell holds a word
False
In memory chips, a decoder is used to select a bit line
False
In memory hierarchy, fast static memories are farthest from the processor.
False
In nested interrupts, current priority level of interrupts is held in processor control register
False
In order to save the contents of 3 registers on the stack, a programmer has to write an instruction to add 12 (decimal) to the stack pointer in order to create space for the saved values.
False
In some of the instructions, step-2 (of a five stage processor) is optional (meaning, no action is taken in step-2).
False
In synchronous DRAM (SDRAM) chips, the mode register cannot be initialized to generate control signals such as Column Address Strobe.
False
In synchronous DRAM typically, it takes longer to activate the selected row than to activate the selected column to access data.
False
In the 2's complement method for representing negative numbers, there are two (2) different ways of representing 0.
False
Keyboard status register holds the data to be transferred to processor
False
Main memory is the slowest component in the memory hierarchy
False
Memory Controller (MC) initiates periodic Read cycles to refresh the cells of Synchronous DRAM.
False
Memory Function Completed (MFC) is needed only during memory access stage (step 4)
False
Memory-mapped I/O devices do not share the memory address space with main memory
False
No action is taken in fifth stage of an 'Add' instruction.
False
Object files from a high-level language and assembly language cannot be combined.
False
Operating system does not allow multitasking.
False
Parameters can not be passed in registers or processor stack (PS)
False
Program-controlled I/O (polling) is better than Interrupts when I/O devices are very slow
False
Program-controlled I/O technique of exchanging data between the processor and I/O device do not use polling to check I/O device status.
False
Setting of the control signals does not depend upon the contents of the instruction register.
False
Stack is also known as first-in-first-out (FIFO) stack
False
Static memories usually have longer access times (than dynamic memories)
False
Subcircuits of a multi-stage processing system are smaller to allow longer clock period.
False
Subroutine calls have smaller address range than a branch instruction.
False
Synchronous DRAMs rely on external controllers for refreshing the cells.
False
The ALU decodes the instruction.
False
The Linker combines source files into object program.
False
The cache is a small and very fast memory between secondary storage and main memory.
False
The instruction Return-from-subroutine uses all the five stages of the processor.
False
The instruction address generator only generates the addresses for a straight-line execution by incrementing program counter (PC) by 4.
False
The inter-stage registers of the datapath are enabled selectively depending upon the type of the instruction.
False
The output file generated by a compiler goes to the loader.
False
The processor status register (PSR), contains information about interrupts that have not been serviced
False
The program counter, PC, counts how many times you have run your program.
False
The routine executed in response to an interrupt is called subroutine
False
The setting of the control signals does not depend upon the result of the comparison operation.
False
To service nested interrupts, IENABLE register is saved to IPENDING register
False
Trace and Breakpoints modes are associated with the Linker.
False
We can write an interrupt service routine (ISR) as a normal function in C language.
False
When fetching an instruction from memory, the program counter (PC) can be enabled without waiting for a Memory Function Complete (MFC) signal.
False
When searching for a block in a cache, if tag matches but valid bit is 0, it is still a hit.
False
Write operation of Read-only memory (ROM) is similar to random access memory (RAM).
False
Write-back is fast and does not involve unnecessary write operations.
False
During the execution of an Interrupt Service Routine (ISR) the I/O device is informed that its request has been recognized and interrupt request is removed. Why?
To prevent further interrupts for the same task
#define statements in C are similar to EQU for associating a symbolic name with an number such as an address.
True
A Call instruction is a special type of branch instruction
True
A DRAM cannot respond to read or write requests while an internal refresh operation is taking place.
True
A branch instruction loads a different value into PC instead of incrementing contents of PC by 4.
True
A control signal is needed to indicate that memory function has been completed.
True
A fixed size virtual memory block is called a page.
True
A library is a collection of commonly used object files.
True
A programmer has located a variable called A at address 0x1000, using a statement A: .skip 68000 to indicate that there will be 68000 bytes of data stored in memory starting at A. If the programmer puts the value 0x1000 in register R4, this statement ldw r3, 4000(r4) will let the programmer fetch the byte at address 0x1000+4000(decimal). Hint: Convert 4000 to hex or binary.
True
A read-only memory (ROM) has its contents written only once, at the time of manufacture.
True
Access circuitry of a register file enables data read from two registers at the same time.
True
After a MEM_read or a MEM_write command is issued, it does not end until the Memory Function Complete (MFC) signal is asserted.
True
All parts of an operating system (OS) are located on disk.
True
All the fives stages of a processor are used by the 'Load' instruction.
True
An Assembler places labels and names in a symbol table as it performs its work.
True
An operating system coordinates all activities in a computer system.
True
An optimizing compiler applies techniques to enhance run-time performance and/or reduce code size.
True
Assembly language programs must be translated into machine language code before execution by the computer.
True
Assembly-language programming requires knowledge of machine-specific details.
True
Asynchronous Dynamic DRAMs do not use a clock signal
True
Asynchronous Dynamic DRAMs do not use a clock signal.
True
Cache memory may have multiple levels.
True
Call instruction stores updated PC contents in Link register (ra) before branching to target (subroutine) address
True
Cells of a programmable ROM (PROM) chip may be written after the time of manufacture.
True
Chip-select (CS) control signal on an individual memory chip facilitates combining of multiple smaller chips to achieve a larger memory.
True
Clearing interrupt enable (IE) bit of processor status register (PSR) prevents all devices from interrupting the processor
True
Compiler automates various tedious tasks, such as managing stack frames.
True
Contents of instruction register (IR) are used to generate all control signals so they must be held until instruction execution is completed.
True
Control Signals (CS) are used to ensure that actions take place in the correct sequence and at the correct time.
True
Control Signals (CS) can also be generated using a Microprogramming approach.
True
Data input port (C) of register file (shown) is connected to output of the last stage of the processor (i.e register RY).
True
Direct mapping is easy to implement.
True
During a memory access, a Wait for Memory Functioned Complete (WMFC) control signal has to be generated.
True
Dynamic RAMs have density/cost advantage over Static RAMs
True
Dynamic RAMs have density/cost advantage over Static RAMs.
True
For a read hit, main memory is not involved; the cache provides the desired information directly to the processor.
True
For both, Branch and Conditional Branch instructions, no action is taken in stage-4 and stage-5.
True
For higher density, Flash cells are designed to be erased in larger blocks, not individually.
True
IPS register is where processor status register (PSR) is automatically saved when an interrupt request is recognized
True
If a 32-bit quantity 0x80000002 is arithmetically shifted to the right by 1 bit position, the result will be 0xC0000001.
True
If a 32-bit quantity 0x80000002 is logically shifted to the right by 1 bit position, the result will be 0x40000001.
True
If a 32-bit quantity 0xCE0FF0FA is rotated to the right by 8 bits, the result will be 0xFACE0FF0.
True
Improved cache performance is dependent on how frequently requested information is found in the cache.
True
In 'Load' instructions, memory is accessed twice.
True
In 'Vectored Interrupts', addresses of subroutines are called interrupt vectors
True
In Dynamic RAMs, burst length determines number of memory transfers.
True
In a Branch instruction, no action is taken in stage 4 and stage 5.
True
In a branch or subroutine call instruction, the new address is loaded into the program counter (PC) after the PC is incremented by 4.
True
In a five-stage processor, the first step is always the same for all instructions.
True
In a multistage processor, clock cycle is determined by the longest path.
True
In a pipelined processor organization, each step is carried out in a separate hardware stage.
True
In a processor, instruction processing consists of two main phases: the fetch phase and the execution phase.
True
In a set-associative cache, associative search involves comparison of tags in a particular set.
True
In a singe pass assembler, some instructions may remain incomplete immediately after the pass completes.
True
In an assembly language program, the programmer indicates the first instruction with a special address label such as START.
True
In associative mapping, larger tag is stored in cache with each block.
True
In associative mapping, new block replaces existing only if the cache is full.
True
In context of writing information from cache to main memory, a single memory update is often more efficient, even if writing back unchanged words.
True
In dynamic RAM chips, address lines may be multiplexed to reduce the pin count
True
In dynamic RAM chips, address lines may be multiplexed to reduce the pin count.
True
In memory chips, the Sense/Write circuits are interfaces between internal bit lines and data I/O pins of the chip
True
In memory chips, the pin count usually dictates the cost
True
In nested subroutines, Link register (ra) contents are overwritten after second subroutine call
True
In nested subroutines, after return from second subroutine, first subroutine restores link register
True
In synchronous DRAM (SDRAM) chips, burst length is specified by initializing a mode register.
True
In typical memory chips, each row of cells constitutes a memory word.
True
Interrupt service routine (ISR) may not have any relation to interrupted program
True
Interrupt-service routine (ISR) and subroutine are not same
True
Locations associated with memory-mapped I/O devices are accessed with Load and Store instructions similar to instruction for memory access
True
Memory hierarchy exploits the principle of locality of reference.
True
Memory-mapped I/O enables software to view the I/O interface registers as locations in memory
True
No action is taken in fifth stage for a 'Store' instruction.
True
Not all programming errors are detected by the compiler; some may be detected by the assembler or the linker.
True
One of the advantages of CMOS cell is that it has low power consumption
True
Pipelined processor organization is most effective if all instructions can be executed in the same number of steps.
True
Processor has stack pointer (SP) register that always points to top of the processor stack
True
Program counter (PC), instruction register (IR) and register file registers are enabled selectively.
True
Read operation of Read-only memory (ROM) is similar to random access memory (RAM).
True
Replacement is trivial for direct mapping.
True
Routines written in assembly language can call high-level language routines, and vice-versa.
True
Row Address Strobe (RAS) and Column Address Strobe (CAS) control signals are used for timing to latch row or column addresses
True
Row Address Strobe (RAS) and Column Address Strobe (CAS) control signals are used for timing to latch row or column addresses.
True
Saving data in a processor register is faster than saving it on stack
True
Setting of the control signals depends upon the contents of the step counter.
True
Shared data connections need tri-state circuits.
True
Since an interrupt service routine (ISR) is similar to a subroutine, saving and restoring of general-purpose registers should be performed
True
Slower dynamic memories have more capacity (than static memories).
True
Static and dynamic RAM chips are volatile.
True
Static memories need power to retain state
True
Synchronous DRAM reduces delay by having the Column Address Strobe (CAS) signal assertion once for initial column address.
True
Synchronous DRAMs include a clock signal.
True
The Debugger makes use of interrupts to help identify programming errors.
True
The Memory Function Completed (MFC) signal is needed because memory access may take longer than one cycle.
True
The Program Counter register (PC) keeps track of the address of next instruction to be fetched and executed.
True
The clock period must be long enough to allow the combinational circuit in a stage to produce the correct result.
True
The density of Static RAMs is lower than the density of Dynamic RAMs
True
The density of Static RAMs is lower than the density of Dynamic RAMs.
True
The instruction stw r3, 0(r7) stores the value in r3 in memory at the address whose value is in r7.
True
The operation of the processor's hardware components is governed by the state of control signals (CS).
True
The order in which the bits in IPENDING are checked establishes a priority for the interrupting devices in case of simultaneous requests.
True
The output of some of the multiplexers in the datapath need not change from one timing step to another.
True
The processor can read the source registers of instructions in step 2, while it is still decoding the OP code.
True
The processor uses the address lines to specify memory location.
True
The setting of the control signals within a processor depends upon the state of interrupt requests.
True
The use of the volatile qualifier in a C language program prevents unwanted compiler optimizations.
True
The Step counter keeps track of instruction execution progress, one clock cycle for each of the five steps except when
data or instruction is accessed from main memory
Access time of serial access devices (such as disk storage devices) is
dependent on location.
In assembly language, mnemonics (LD, ldw, ADD etc.) represent the:
destination register Correct Answer op code operand source register
For a conditional branch instruction, a separate comparison circuit is used instead of subtraction using ALU:
ecause subtraction is time consuming and should be avoided. to make comparison fast to make clock cycle short Correct Answer all choices are correct
An I/O device interface provides means for
exchange of status only Correct Answer data transfer, exchange of status and control information data transfer only control information only
If a page is in memory, the page table raises an interrupt to involve operating system.
f
In Virtual Memory, translation preserves offset bits, but causes Virtual Page Number (VPN) bits to be replaced with page frame bits
f
Memory management unit (MMU) holds the page table.
f
Programs intended for a computer system implementing virtual memory are written keeping in mind the physical storage of the computer.
f
Translation lookaside buffer (TLB) holds the page table.
f
Which of the following functions is not performed by the processor as it executes instructions:
convert source code to machine code
Memory hierarchy exploits program behavior to make it appear as though memory is
fast and large.
Memory hierarchy is a structure that uses multiple levels of memories such that
fast and small memory is closer to the processsor.
The block transfer capability of a dynamic RAM is called
fast page mode
In the figure shown, input 1 of MuxMA is selected when:
fetching instruction from memory
In stack, elements are added/removed
from bottom end only from either end from the middle Correct Answer from top end only
Indirect addressing mode provides the address
from the origin of program data Correct Answer in a processor register in a register with an offset value as an immediate value
Subroutines are useful when you want to
implement same task many times on different data make your program easy to manage Correct Answer all the three choices are correct make your program modular
One of the defining characteristics of Synchronous RAM is
inclusion of clock signal.
Major advantage of a static RAM is that
it is fast.
Major advantage of a dynamic RAM is that
it is larger and cheaper.
In a computer system with k address lines (k bits), the directly addressable memory range is from
k to 2^k-1 1 to 2^k-1 None of the other three choices are correct Correct Answer 0 to 2^k-1
What is the main advantage of cache memory?
large storage capacity retains data when the power is off (non-volatile) Correct Answer fast speed (less access time) slow speed (more access time)
Writing to a processor register is involved in the execution of following instructions:
load and add.
Which of the following is not a part of the processor?
main memory
Dynamic RAMs are typically used for
main memory.
When a subroutine is called, the return address
may not be saved is saved in program counter (PC) register Correct Answer is saved in link register (ra) is saved in main memory
Setting of the control signals does not depend on
none of the choice is correct
Primary memory (or main memory) of a computer stores:
none of the choice is correct programs data Correct Answer programs and data
Which of the following is NOT a part of the memory hierarchy:
none of the choices is correct.
In response to an interrupt, the return address should be saved
on stack
Assuming the instruction is in the cache, data from one processor stage to the next stage is transferred in
one clock cycle
During the execution of an add immediate instruction:
one source register is read
When an interrupt request is recognized
processor status register (PSR) is automatically saved to IPS register
Cache holds copies of
program instructions and data stored in the large main memory.
In a dynamic RAM, Row Address Strobe (RAS) and Column Address Strobe (CAS) signals
provide timings for address bits
Which of the following is not included in the actions performed by the processor when executing the operation specified by an instruction?
raise interrupt request
In nested subroutines when a subroutine calls another subroutine, the contents of the link register (ra)
remain unchanged should be saved in program counter (PC) need not be saved Correct Answer should be saved on stack
Since Interrupt-service routine (ISR) is similar to that of a subroutine,
saving and restoring of general-purpose registers should be performed during the start of the ISR
Stack is part of
secondary memory processor registers Correct Answer main memory cache memor
In RISC, arithmetic and logic unit (ALU) performs operations on data operands in
secondary memory Correct Answer processor registers cache memory main memory
Interrupt nesting is allowed by having interrupt service routine (ISR)
set the interrupt enable (IE) bit of processor status register (PSR) to 1
Smaller sub-circuits in a multistage processing system requires:
shorter clock period
After an interrupt is detected, Interrupt Enable (IE) bit in Processor Status Register (PSR) is cleared to 0
so that the same or other signal does not cause further interruptions
Which of the following is not a component of an I/O device interface:
status register data register Correct Answer link register control register
In Instruction Address Generator (shown), input 0 of MuxPC is selected for:
subroutine linkage
Since page tables are stored in main memory, each memory access takes twice as long.
t
There is no unique assignment/mapping for a virtual address to physical address.
t
Virtual memory hides physical memory capacity limitations.
t
Write-through, though useful in the cache, is not suitable for virtual memory.
t
Memory Function Completed (MFC) signal is used to show
that the memory read or write has been completed.
For random-access memory (RAM)
the access time is independent of location.
Memory latency is
the amount of time it takes to transfer the first word of a block.
Double-Data-Rate (DDR) SDRAMs are faster because
the data is transferred on rising as well as falling edge of the clock.
Branch offset in a Branch instruction is:
the distance between the Branch target and the memory location following the branch instruction.
Principal of Spatial Locality states that
the instructions/data that are nearby the recently used one, are likely to be accessed again.
Principal of Temporal Locality states that
the instructions/data that have been recently accessed are likely to be accessed again.
Memory cycle time is
the minimum time delay between initiation of successive transfers.
Memory bandwidth is
the number of bits or bytes that can be transferred in one second.
The need of synchronization between the processor and I/O devices arises mainly because of
the speed difference between them
Memory access time is
the time from initiation to completion of a word transfer.
Pipelining enables the execution of successive instructions:
to be overlapped
Which of the following is NOT a type of read only memory (ROM)?
volatile ROM (VROM).
When data is not in the cache
we cannot assume that the memory access will take one cycle.
Mapping function determines
where a block from memory is to be located in the cache.
Replacement algorithm determines
which block to remove from cache when required.
In a 32-bit byte addressable memory, high-order 30 bits determine
which word will be accessed.
In a RAM, cells of a row are connected to a common line referred to as
word line.
Which of the following steps is not involved in the execution of a load instruction?
write to main memory
Which of the following steps is not involved in the execution of an add instruction?
write to main memory
Which of the following steps is not involved in the execution of a store instruction?
write to processor register
Which of the following is NOT an example of Flash memory:
cache
What is the 8-bit representation of -1 in 2's complement?
-0000001 11111110 Correct Answer 11111111 10000001
What is the 8-bit representation of -2 in 2's complement?
-0000010 11111101 10000010 Correct Answer 11111110
Convert the following pairs of decimal numbers to 5-bit 2's-complement numbers, then add them. What is the answer: -13 and 12
01001 Correct Answer 11111 10101 1101
What is sum of following operation of signed binary numbers 0 1 1 0 + 0 0 1 0 ------------
0101 1010 Correct Answer 1000 0011
Suppose that register r2 initially contains 0x23456789. After the following program is run on a little-endian system where R0 contains zero, what will register R3 contain:
0x00000089 0x00000000 0x00000023 Correct Answer 0xFFFFFF89
The following value 0x11223344 is stored in a 32-bit word at address 0x2000. If the computer is little-endian, the contents of the byte at 0x2000 is:
0x11 0x22 0x33 Correct Answer 0x44
The following value 0x11223344 is stored in a 32-bit word at address 0x2000. If the computer is big-endian, the contents of the byte at 0x2003 is:
0x22 0x33 Correct Answer 0x44 0x11
The following value 0x11223344 is stored in a 32-bit word at address 0x2000. If the computer is big-endian, the contents of the byte at 0x2000 is:
0x33 0x22 0x44 Correct Answer 0x11
Convert the following pairs of decimal numbers to 5-bit 2's-complement numbers, then subtract the second number from first number. What is the answer: -4 and +8
10111 00100 11101 Correct Answer 10100
What is the 8-bit representation of -127 in 2's complement?
11111110 -01111111 Correct Answer 10000001 11111111
Which one of the following is NOT a valid way for representation of signed integers:
2's complement 1's complement Sign and magnitude Correct Answer 0's complement
In a 32-bit word, word aligned byte addressable memory, the program counter (PC) register is incremented by:
4 2 1 3
Which of the following is NOT a typical control pin connection in a RAM
Address.
Service routines for I/O devices are part of the operating system.
Alec
Given that the contents of display status register (as shown) have been copied to register R4, which of the following instructions will you use to check if the display is ready to accept data (i.e DOUT=1) ?
And R4, R4, #4
Load and Store Instructions
Are used to copy data from one register to another register. All of the above. Correct Answer Are used to copy data to and from memory locations. Use Immediate mode to determine the Effective Address.
Following bits of instruction register (IR) are connected to address A of the processor register file:
Bits 31-27
Question 334 Unsaved Step 4 and 5 have 'No action' associated with following instructions:
Branch, conditional branch, return and jump instructions.
Step 4 and 5 have 'No action' associated with following instructions:
Branch, conditional branch, return and jump instructions.
Suppose register R2 contains 0xFFFFFFFE and register R3 contains 0x00000001. What is the result if R2 is subtracted from R3?
Correct Answer 0x00000003 0xFFFFFF11 0xFFFFFFFD 0xFFFFFFFF
Suppose register R2 contains 0xFFFFFFFD and register R3 contains 0x00000002. What is the result if R2 is subtracted from R3?
Correct Answer 0x00000005 0xFFFFFF12 0xFFFFFFFF 0xFFFFFFFB
The following value 0x224488CC is stored in a 32-bit word at address 0x2000. If the computer is little-endian, the contents of the byte at 0x2000 is:
Correct Answer 0xCC 0x22 0x44 0x88
The decimal equivalent of 0xA1 is:
Correct Answer 161 163 159 160
The decimal equivalent of 0xCC is:
Correct Answer 192 168 180 198
In a generic assembly language, a program for the calculation C=A+B is written as:
Correct Answer Load R2, A Load R3, B Add R4, R2, R3 Store R4, C Load R2, A Load R3, B Add R2,R4, R3 Store R4, C Load R2, A Load R3, B Add R4, R2, R3 Store C,R4 Load A,R2 Load B,R3 Add R4, R2, R3 Store R4, C
Which of the following is NOT part of the processor?
Correct Answer complete stack registers arithmetic and logic unit (ALU) program counter
Instruction register (IR) register contains the following information:
Correct Answer current instruction being executed next instruction to be executed address of the current instructions being executed. address of the next instruction to be executed.
Passing parameters through registers is simple but it has the drawback that it is
Correct Answer limited to available registers prone to data corruption slow fast
A 'Read' operation does not 'refresh' a dynamic RAM
False
A 'Read' operation does not 'refresh' a dynamic RAM.
False
A processor must always respond immediately to interrupt-service routines (ISR)?
False
A programmer has located a variable called A at address 0x1000, using a statement A: .skip 68000 to indicate that there will be 68000 bytes of data stored in memory starting at A. If the programmer puts the value 0x1000 in register R4, this statement ldw r3, 40000(r4) will let the programmer fetch the byte at address 0x1000+40000(decimal). Hint: Convert 40000 to hex or binary.
False
Access time of serial access devices (such as magnetic tape) does not depend on the address or position of the data
False
Addresses inputs A and B of Register File (shown) come from the Address Generator.
False
After acknowledging and servicing interrupt, interrupt enable (IE) bit of processor status register is cleared to 0 again.
False
An Assembler translates an object file to source code.
False
Associative mapping (for cache) does not require replacement algorithm.
False
Branching back to a label is an example which needs 'two-pass' approach of the assembler.
False
Cache block (cache line) refers to a set of non-contiguous address locations of some size.
False
Cache holds currently active portions of a program instructions only but not the data
False
Cache is used to bring only the data that is about to be used as close to the processor as possible ( i.e. it is not used for instructions).
False
Cache memory is a faster and larger than the main memory.
False
Compilers do not permit inclusion of assembly language instructions in high-level languages.
False
Contents of stack pointer (SP) remain fixed during Pop and Push operations
False
Data lines are used to specify address location.
False
Direct mapping is flexible offering efficient use of space.
False
During execution of 'Call' instruction, program counter (PC) is updated to point to instruction before the 'Call'
False
During the instruction fetch cycle (stage 1), the processor doesn't need to wait for the Memory Function Complete (MFC) signal.
False
Dynamic RAMs do not need periodic 'refreshing' to recharge.
False
Fast page mode of dynamic RAMs is not suitable for main memory data transfers.
False
For a conditional branch instruction, comparison and testing of the condition is done in separate stages.
False
For arithmetic operations, the immediate value is zero-padded; for others, (logic instructions), it is sign-extended.
False
For nested interrupts, IPS register need not be saved
False
For the 'Add Immediate' instruction, the immediate value is given in a processor register.
False
If one 32-bit word in byte-addressable memory is at address 0x1010, then the next word will be at 0x1011.
False
If the instruction being executed is the cause of the exception, it is allowed to complete before service routine can be executed
False
If you know the contents in binary format of a word in memory, and you know that the word does not contain an instruction, then you can, by just examining the contents, determine whether the contents are real data or a pointer to real data.
False
If you know the contents in binary format of a word in memory, then you know whether it is an instruction or data.
False
In 'Add' instructions, memory is accessed twice.
False
In SDRAMs, the time to transfer successive words of a block is much longer than time needed to transfer the first word.
False
In a 32-bit byte addressable system, stack pointer (SP) is incremented and decremented by 2 during POP and Push operations
False
In a Branch or Jump instruction, return address is saved in the link register (ra).
False
The instruction fetched from main memory is placed in the:
Instruction Register (IR)
In ALU stage 3 (shown), input 1 of MuxB comes from:
Instruction register (IR)
Two address inputs to the register file are connected to:
Instruction register (IR).
The program that handles interrupt requests and provide the corresponding service to the requesting devices are often referred to as the
Interrupt Handler
Which of the following statements is valid for vectored interrupts:
Interrupt vector table is located at fixed address, but interrupt service routines can be located anywhere in memory
In the memory stage-4 (shown), input 2 of MuxY is selected for:
Interrupts
Absolute addressing mode is limited to
It does not have any limitation Correct Answer 16 bits 32 bits 8 bits.
Which of the following is NOT true about cache memory Data transfer between main memory and cache is done using
It is cheaper than main memory. blocks of data.
After the data is read from keyboard data register (KBD_DATA), why is it important to clear the data-in (KIN) bit ?
It prevents the processor to read the same data again
Register R5 is used in a program to point to the top of a stack containing 32-bit numbers. What would be the correct sequence of instructions to copy the fifth item from the top into register R3.
Load R3←16(R5) Load 16(R5), R3 Load R3, 5(R5) Correct Answer Load R3, 16(R5)
In stack, 'Pop' operation involves following instructions
Load Rj, SP Add SP, SP, #4 Add SP, SP, #4 Load Rj, (SP) Load Rj, (SP) Subtract SP, SP, #4 Correct Answer Load Rj, (SP) Add SP, SP, #4
In the Memory stage 4 (shown), input 1 of MuxY is selected in:
Load instruction
For an 8 bit I/O device status register (KBD_STATUS), the best assembly language instruction for loading its contents in register R2 would be
LoadByte R2, KBD_STATUS
On receiving interrupt, which of the following is automatically performed by the processor:
Loads the address of first instruction of interrupt service routine into program counter (PC) Correct Answer All the three choices are correct Saves program status register (PSR) and clears interrupt enable (IE) bit Saves program counter (PC) register
What is the difference between Load/Store instructions and Move instructions?
Move instructions are faster. Correct Answer Load/Store are used to move data from and to memory; Move only moves data between registers. There is no difference. Move instructions are slower
Which of the following assembly language instruction is correct for transferring desired bit pattern in R3 to processor control register IENABLE
MoveControl IENABLE, R3
Parameters can be passed to subroutines:
Only via processor registers. Only via values pushed onto the stack. Correct Answer Via both processor registers and values pushed onto the stack. Parameters can only be passed to subroutines by writing values into fixed locations in memory.
Given that the contents of processor control register IENABLE (as shown) have been copied to register R2, chose the correct instruction for enabling interrupts for both keyboard and display devices
Or R2, R2, #6
In step 3 of 'Call with indirection' instruction, contents of the program counter (PC) are stored in register 'PC-Temp' and then contents of inter-stage register RA are stored in PC. In RTN, it is represented as follows:
PC-Temp← [PC], PC←[RA]
PC_enable signal is set to 1 only when MFC is received while fetching an instruction and also in step 3 of instructions that cause branching. This control signal can be written as
PC_enable = T1 ・ MFC + T3 ・ BR
What is the major advantage of Interrupts as compared to Program-controlled I/O (Polling)?
Processor can perform useful tasks when IO device is not ready
Which of the following statement is true about processor registers?
Processor registers are fastest, but do not use the same address space as the main memory.
Due to the latency involved in saving and restoring registers, usually following are saved in response to an interrupt:
Processor status register (PSR) and program counter (PC)
Processor fetches the contents of the memory location pointed to by:
Program Counter (PC)
To provide non-volatile storage, following type of memory is used:
Read-only memory (ROM).
In assembly language, use of constants is provided by the following addressing mode:
Register Register indirect Absolute Correct Answer Immediate
Why is it important to remove the interrupt request from I/O device after it has been acknowledged?
So that processor is not bothered for the same interrupt again
In stack, 'Pop' operation involves following instructions
Store Rj, (SP) Subtract SP, SP, #4 Correct Answer Subtract SP, SP, #4 Store Rj, (SP) Subtract SP, SP, #1 Store Rj, (SP) Add SP, SP, #4 Store Rj, (SP)
In stack, 'Push' operation involves following instructions
Store Rj, (SP) Subtract SP, SP, #4 Correct Answer Subtract SP, SP, #4 Store Rj, (SP) Subtract SP, SP, #1 Store Rj, (SP) Add SP, SP, #4 Store Rj, (SP)
The current stack frame refers to:
The 16 words starting at the location pointed to by sp. Correct Answer The portion of the stack that is relevant to the currently executing subroutine. The memory block pointed to by the fp register at one end and the sp register at the other end. The boundary around the processor stack
If a Write signal is set to 1 during step 5 for Add, Load or Call instruction, its control signal can be written as
Write = T5 ・ (ALU + Load + Call)
For Load/Store operations, we assumed that memory Read and Write operations can be completed in one clock cycle. Is this a realistic assumption?
Yes, if the data is in the cache
Express following high level language instruction to register transfer notation (RTN): C=A+B
[C]←[A]+[B] C←A+B Correct Answer C←[A]+[B] [C]←A+B
Instructions are fetched from successive memory locations until:
a branch instruction is met Correct Answer all choices are correct a subroutine call instruction is met a jump instruction is met
An I/O device interface is a
a circuit between a device and the main memory a circuit inside the processor Correct Answer a circuit between a device and the interconnection network a circuit between a device and the secondary storage
For arithmetic and logic (ALU) instructions, data contents may come from:
a processor register and an immediate value in the instruction a processor register two processor registers Correct Answer all choices are correct
During a read request, if the desired data is in the cache
a read hit occurs.
During a read request, if the desired data is not in the cache
a read miss occurs.
During a write request, if the desired data is in the cache
a write hit occurs.
During a write request, if the desired data is not in the cache
a write miss occurs.
Program counter (PC) register contains the following information:
address of the current instructions being executed. Correct Answer address of the next instruction to be executed. address of the previous instruction just executed. address of processor register r0.
SDRAMs can deliver data at a very high rate, because
control signals are generated inside the chip.
One of the main drawback of 'Program-controlled I/O' is
complex circuitry to implement it extremely fast and processor cannot keep up with it Correct Answer waste of processor time too much overhead
How can the control hardware know which register to read before it has completed decoding instruction?
because source register addresses are known in advance. because source register addresses are specified using the same bit positions in all instruction.
In a RAM, cells of a column are connected to a common line referred to as
bit line.
Data transfer between main memory and secondary storage is done using
blocks of data.
To provide finer control over interrupts and flexibility to the programmers,means of interrupt enabling and disabling are provided
both in processor and in I/O device interfaces
In the Instruction Address Generator, the program counter (PC) is not incremented by 4 for:
branch instruction
Static RAMs are typically used for
cache
