final exam

89. What voltage level(s) signify a logical zero in RS-232 ?

+3 to +15V

66. What is the meaning of the term "19.2k Baud Rate" in serial communications ?

19,200 bits per second

84. At 19.2 kBaud, how long does it take to transmit 1920 bytes serially, when each byte requires 2 framing bits (start, stop) ?

1920 bytes * 10 bits/byte / 19,200 bits/sec = 1 second

90. What is the difference between synchronous serial and asynchronous serial digital communication systems ?

Asynchronous has no clock wire, whereas synchronous includes a clock

91. Explain the difference between half-duplex and full-duplex serial lines ?

Half-duplex sends and receives data on the same wire, not at the same time. Full duplex has 2 wires and simultaneous send/receive.

56. What are the other three resistor values if the LSB resistor of a binary-weighted resistor DAC is 48K? a. 24K, 12K, 6K b. 96K, 192K, 384K c. 36K, 24K, 16K d. 24K, 16K, 8K

a. 24K, 12K, 6K

65. How many clock pulses does an 8-bit successive-approximation ADC require to convert a maximum input? a. 8 b. 16 c. 64 d. 256

a. 8

Which potential problem must be overcome when interfacing TTL to CMOS? a. HIGH output voltage may be too low b.HIGH output voltage too high. c. output current may not be sufficient d.LOW output voltage too high.

a. HIGH output voltage may be too low

Automatic reset circuitry for digital devices usually use a. RC circuits. b. complex ICs. c. setup time. d. toggle states.

a. RC circuits.

51. Which of the following, along with appropriate R and C, makes for a simple astable multivibrator? a. Schmitt inverter b. TTL inverter c. Single NAND gate d. Single flip-flop

a. Schmitt inverter

58. What is the unique feature that characterizes the R/2R ladder D/A converter? a. There are only two sizes of resistor. b. All resistors are the same size. c. It can only handle four bits maximum. d. Each resistor must be a different size.

a. There are only two sizes of resistor.

80. When more than one memory IC is used in a system, a technique called __________ __________ is used to identify which IC is being accessed. a. address decoding b. memory refresh c. data encoding d. memory paging

a. address decoding

73. Which signal path connecting the memory to the microprocessor is bidirectional? a. data bus b. address bus c. control bus d. all of the above

a. data bus

One advantage that MOSFET transistors have over bipolar transistors is a. high input impedance. b. higher switching speed. c. low input impedance. d. reduced propagation delay.

a. high input impedance.

38. A ring counter is a shift register that a. recirculates one HIGH bit continuously through each flip-flop. b. shifts until all flip-flops are HIGH. c. shifts until all flip-flops are LOW. d. connects each flip-flop output to the shift register input.

a. recirculates one HIGH bit continuously through each flip-flop.

The output current for a LOW output is called a a. sink current b. ground current. c. exit current d. fan-out.

a. sink current

Typical TTL LOW level output voltage is a. 0.0 V. b. 0.3 V. c. 3.4 V. d. 4.0 V.

b. 0.3 V.

Which of the following levels would not be a valid LOW for a TTL gate? a. 0.1 V b. 1.0 V c. 0.7 V d. All are valid.

b. 1.0 V

How many flip-flops are required to make a counter which counts from 0 to 7? a. 2 b. 3 c. 4 d. 5

b. 3

48. An astable 555 timer is designed using the following external components: RA = 2K, RB = 6.5 K, C = .01uF. Calculate time LOW (tLO). a. 550usec b. 45usec c. 325 msec d. 105usec

b. 45usec

34. What else distinguishes synchronous counters from asynchronous counters? a. Synchronous counters never use the TOGGLE mode. b. A common clock is tied to the clock input of all flip-flops in a synchronous counter. c. J and K inputs of each flip-flop in a synchronous counter are tied HIGH. d. Synchronous counters do not use J-K flip-flops.

b. A common clock is tied to the clock input of all flip-flops in a synchronous counter.

If data is brought into the J terminal and its complement to the K terminal, a J-K flip-flop operates as a(n) a. S-R flip-flop. b. D flip-flop. c. gated S-R flip-flop. d. TOGGLE flip-flop.

b. D flip-flop.

30. Describe the relationship between the frequency of the clock and that of the Q output of a J-K flip-flop configured in the TOGGLE mode. a. It multiples by 2. b. It divides by 2. c. It divides by 4. d. They have no relationship.

b. It divides by 2.

64. What advantage does a successive-approximation ADC have over the counter ADC? a. It uses less costly components. b. It has faster conversion times. c. It uses fewer components. d. All of the above are correct.

b. It has faster conversion times.

Where is the least significant Q output connected on a binary ripple counter? a. J input of the next flip-flop b. K input of the next flip-flop c. SET input of the next flip-flop d. clock of the next flip-flop

b. K input of the next flip-flop

32. Two 7490 decade counters, configured to count 0 to 9, are connected so that the Q3 output of one IC is wired to the clock input of the other IC. What is the modulus of the total circuit? a. MOD-99 b. MOD-100 c. MOD-20 d. MOD-80

b. MOD-100

A data storage device constructed using two NAND gates or two NOR gates is the a. multiplexer. b. S-R flip-flop. c. J-K flip-flop. d. encoder.

b. S-R flip-flop

44. Which components are added to a monostable multivibrator to determine the specific time durations required at the output? a. two resistors b. a resistor and a capacitor c. an AND gate and an OR gate d. a resistor and a diode

b. a resistor and a capacitor

A difference between a Schmitt trigger and a standard TTL gate is that a. a standard gate is slower than a Schmitt trigger. b. a standard gate has a lower switching threshold for positive-going inputs. c. a standard gate has lower voltage outputs. d. a Schmitt trigger input must be exactly 5.0 V or it will be ignored.

b. a standard gate has a lower switching threshold for positive-going inputs.

42. Which specialized TTL circuit allows several devices to be connected to its output simultaneously? a. a Schmitt trigger circuit b. a three-state device c. a shift register d. a Schottky device

b. a three-state device

36. Decoders used to drive common-anode LEDs must have a. active HIGH outputs. b. active LOW outputs. c. a blanking output. d. low ripple characteristics.

b. active LOW outputs.

78. Dynamic memories such as the 2118 16K X 1 RAM have to multiplex the a. data bus. b. address bus. c. control bus. d. All of the above are correct.

b. address bus

The time the input must be steady after a clock pulse occurs is known as a. setup time. b. hold time. c. race time. d. propagation delay.

b. hold time.

35. The propagation delays of the flip-flops in a counter determine the a. modulus. b. maximum frequency. c. ripple sequence. d. number of flip-flops.

b. maximum frequency.

The output stage of a TTL gate is a special design called a. multiemitter b. totem-pole. c. MSI d. DIP.

b. totem-pole

60. What is the major advantage of the parallel ADC? a. very high resolution b. very fast conversion times c. low component cost d. low component count

b. very fast conversion times

37. A parallel-in, serial-out shift register is loaded initially with 1100. What will the register contain after two clock pulses if the serial input is LOW? a. 1110 b. 0001 c. 0011 d. 0000

c. 0011

Fan-out for a typical TTL gate is a. 100 b. 54. c. 10 d. 4.

c. 10

71. A 4K X 1 RAM requires __________ address bits to access all locations. a. 4096 b. 10 c. 12 d. 1024

c. 12

What is the maximum value out of a binary counter which has four flip-flops? a. 3 b. 7 c. 15 d. 16

c. 15

59. What is Vout of a 4-bit R/2R Ladder DAC if the binary input is 1000 when the reference voltage is 5 V, R is 8K, and Rf is 16K? a. 2.25 V b. 4.75 V c. 5 V d. 6.25 V

c. 5 V

61. Which of these components is not part of an eight-bit counter ADC? a. a MOD-256 counter b. octal D flip-flop c. 8-to-3 bit encoder d. 8-bit DAC

c. 8-to-3 bit encoder

79. Which memory is nonvolatile yet can be altered and reprogrammed? a. ROM b. RAM c. EPROM d. dynamic RAM

c. EPROM

Which type of flip-flop is referred to as "one's catching"? a. D b. R-S c. J-K d. Toggle

c. J-K

Why is it difficult to drive a light-emitting diode with a standard TTL gate? a. LED threshold voltage is too high. b. LED devices are CMOS logic. c. LED devices draw too much current. d. LED devices are too slow for TTL switching speeds.

c. LED devices draw too much current

A counter which counts from 0 to 6, then recycles to 0, is what modulus ? a. MOD-5 b. MOD-6 c. MOD-7 d. MOD-8

c. MOD-7

Which of the following is not a common logic family used today? a. TTL b. CMOS c. RTL d. ECL

c. RTL

When outputs of a NOR-gate SR flip-flop are Q = 0 and -Q = 1, the inputs are a. S = 1, R = 1. b. S = 1, R = 0. c. S = 0, R = 1. d. S = 0, R = 0.

c. S = 0, R = 1.

If the inputs of a J-K flip-flop are J = 1 and K = 1, what will the flip-flop do on the next clock pulse? a. SET b. RESET c. TOGGLE d. HOLD

c. TOGGLE

57. Why is a binary-weighted resistor DAC impractical when over four bits of resolution are needed? a. Too much current is demanded from the power supply. b. Not enough voltage can be generated by the power supply. c. Too many odd resistor sizes are required. d. It becomes too difficult to calculate the voltage output.

c. Too many odd resistor sizes are required.

75. Which memory operation is needed only on dynamic memory? a. a read cycle b. a write cycle c. a refresh cycle d. chip select

c. a refresh cycle

When the outputs of several open-collector TTL gates are connected, they a. usually burn out. b. produce more voltage. c. are effectively ANDed together. d. produce more fan-out.

c. are effectively ANDed together.

43. Which multivibrator is a free-running oscillator with a square-wave output? a. bistable b. monostable c. astable d. all of the above

c. astable

31. The 7492 MOD-12 ripple counter is made up of two internal counters. They are a. divide-by-2 and divide-by-4. b. divide-by-2 and divide-by-5. c. divide-by-2 and divide-by-6. d. divide-by-2 and divide-by-8.

c. divide-by-2 and divide-by-6.

A positive level-triggered flip-flop will only accept inputs when the clock a. is LOW. b. changes from HIGH to LOW. c. is HIGH. d. changes from LOW to HIGH.

c. is HIGH.

69. Dynamic memory is memory a. that will maintain storage even if power is removed. b. whose data can never be altered. c. that must be refreshed periodically or it will lose storage. d. that maintains storage as long as power is applied.

c. that must be refreshed periodically or it will lose storage.

63. A counter-ramp ADC uses a comparator to compare the input voltage with a. a binary number. b. the output of a counter. c. the output of a DAC. d. a voltage divider network

c. the output of a DAC.

The major drawback of ripple counters is that a. they can only count to 15. b. they can only count to 31. c. the propagation delay is high. d. they can't use J-K flip-flops.

c. the propagation delay is high.

55. If the least significant bit (LSB) of a four-bit binary-weighted resistor D/A converter connects to a 200K resistor, which resistor is needed for the next bit? a. 200K b. 300K c. 400K d. 100K

d. 100K

70. When dealing with computer memory, the term 1K means a. 100. b. 256. c. 1000. d. 1024.

d. 1024.

74. The 2147 4K X 1 static RAM contains 4096 storage locations storing one bit each. How many 2147 chips are needed to configure an 8K X 8 memory system? a. 1 b. 4 c. 8 d. 16

d. 16

62. How many clocks does an 8-bit counter ADC require to convert a maximum input? a. 8 b. 16 c. 64 d. 256

d. 256

67. 8-bit digital representations of analog voltages yield _____ representations. a. 32 b. 64 c. 128 d. 256

d. 256

87. What is the maximum memory supported by a 16-bit Address Bus? a. 1 Mbyte b. 16 Kbyte c. 32 Kbyte d. 64 Kbyte

d. 64 Kbyte

49. If the output of an astable 555 timer is LOW for 2.85 æsec and HIGH for 6.7 æsec, the duty cycle is a. 90%. b. 52%. c. 57%. d. 70%.

d. 70%.

40. What is the Modulus of a 4-bit Johnson Counter? a. 4 b. 16 c. 6 d. 8

d. 8

Which of the following output levels would be a valid HIGH for a TTL gate? a. 5.1 V b. 3.0 V c. 2.6 V d. All are valid.

d. All are valid.

83. Which of the following are non-volatile and electro-mechanical? a. Floppy disk b. Hard drive c. CD-ROM d. All of the above

d. All of the above

82. Which ROM allows erasing and reprogramming a block of memory at a time? a. PROM b. EPROM c. EEPROM d. Flash

d. Flash

52. In astable operation of a 555 timer, which component value can be set to zero? a. RA b. RB c. C d. None of the above

d. None of the above

81. Which of the following would not be found in a PC? a. SIMMs b. DIMMs c. RIMMs d. PIMMs

d. PIMMs

When a NOR gate S-R flip-flop is in the HOLD state (no change), inputs are a. S = 1, R = 1. b. S = 1, R = 0. c. S = 0, R = 1. d. S = 0, R = 0.

d. S = 0, R = 0.

33. What distinguishes synchronous counters from asynchronous counters? a. Synchronous are slower. b. Synchronous can count higher. c. Synchronous are CMOS. d. Synchronous have less delay.

d. Synchronous have less delay.

What makes a TTL gate have an open-collector output? a. The input transistor is replaced by a diode. b. The output transistors are replaced by diodes. c. The output transistors are missing. d. The top output transistor is missing.

d. The top output transistor is missing.

53. Which of the following is not an analog electrical signal? a. a sine wave b. a triangle wave c. a microphone output d. a square wave

d. a square wave

41. Which of these functions are possible in a 74194 Universal Shift Register? a. shift left b. parallel load c. shift right d. all of these

d. all of these

46. Which type of multivibrator configuration is possible using the 555 timer? a. bistable b. monostable c. astable d. both b and c are correct

d. both b and c are correct

77. Dynamic RAMs store information by using a. magnetism. b. flip-flops. c. latches. d. capacitors.

d. capacitors

54. On a binary-weighted D/A converter the least significant binary input a. connects to the smallest resistor. b. supplies the least voltage. c. connects to a 1 K resistor. d. connects to the largest resistor.

d. connects to the largest resistor.

76. The major advantage of dynamic RAM over static RAM is a. cost. b. speed. c. storage density. d. cost and storage density.

d. cost and storage density

39. The characteristic output waveform of a Johnson counter has a. each flip-flop changing states one time. b. one HIGH bit continuously recirculating through all flip-flops. c. a binary count continuing until all flip-flops are HIGH. d. each flip-flop go HIGH one at a time and then go LOW one at a time.

d. each flip-flop go HIGH one at a time and then go LOW one at a time.

The major advantage of CMOS logic circuits over TTL is a. lower propagation delay. b. higher propagation delay. c. produces several output voltage levels. d. low power consumption.

d. low power consumption.

50. Which timing control component gives an oscillator better stability and accuracy than the RC network? a. Schottky diode b. potentiometer c. comparator d. quartz crystal

d. quartz crystal

47. Which formula is correct when calculating time LOW (tLO) for an astable 555 timer output? a. tLO = RBC b. tLO = RARB(.693) c. tLO = RB(.693) d. tLO = RBC(.693)

d. tLO = RBC(.693)

68. Static memory is memory a. that will maintain storage even if power is removed. b. whose data can never be altered. c. that must be refreshed periodically or it will lose storage. d. that maintains storage as long as power is applied.

d. that maintains storage as long as power is applied.

An edge-triggered flip-flop can only change states when a. the trigger is HIGH. b. the D input is HIGH. c. the trigger is LOW. d. the trigger input changes levels.

d. the trigger input changes levels.

72. Which type of outputs do RAM circuits have? a. random b. TTL c. high power d. three-state

d. three-state

45. What is the pulse width (tw) output of a 74121 monostable multivibrator? a. tw = Rext(.693) b. tw = RextRint(.693) c. tw = RintCint(.25) d. tw = RextCext(.693)

d. tw = RextCext(.693)

88. What is the purpose of the start & stop bits in RS-232 serial communications ?

synchronize the receiver to when the data bits begin and end