IT225 Final
A pulse generator connected to a D flip-flop limits the flip flop changing state to when no pulse is present on the enable line. T or F
False
A shifter can shift bits one to the left, but cannot shift bits one to the right. T or F
False
An AND gate has inputs A, B, and C. A and C are high (0). B is low (0). The output of the gate will be high voltage (1). T or F
False
An SR flip-flop in state 0 will change to state 1 upon setting the reset line to 1. T or F
False
Maskable interrupts cannot be interrupted by other interrupts. T or F
False
NOT, NAND, and NOR gates will all output high voltage (1) when all of their input voltages are high (1). T or F
False
SR flip-flop states are named for the value of Q-bar. T or F
False
Stack architecture would utilize a Push instruction to remove data from a stack. T or F
False
Stack architecture would utilize a Push instruction to remove data from a stack. True False
False
Synchronous clock time on buses connected to the CPU almost always match the CPU clock time. T or F
False
Translation occurs in real time, and interpretation takes place solely in advance. A. True B. False
False
A 1 bit ALU is pictured. For questions #1 and #2 below (answer #1 and #2 separately), state which unit in the ALU is activated (options are AND, OR, NOT B, or ADD) and the value of the Output and Carry Out bits. You may skip providing the Carry Out bit value if the ADD operation is not activated. #1 F0=1 F1=0 ENB=1 B=1 #2 F0=0 F1=0 ENA=1 ENB=1 A=1 B=1 INVA=0 Carry_In=0
Feedback: #1 NOT B, Output=0 #2 AND, Output=1
Simplify the following function. Show work for partial credit in case your final answer is incorrect. (AA + ( B + 0CC)1)
Feedback: (AA + ( B + 0CC)1) AA + ( B + 0CC) A + (B + 0CC) A + (B + 0) A + B
Convert .712 base 10 to base 5 using the subtraction method. Show your work for full credit.
Feedback: .712-(.2*3)=.112 .112-(.04*2)=.032 .032-(.008*4)=0 .324
Write the number positive 4 in 8 bit two's compliment (base 2). Convert the number to its negative complement. Afterward, convert the number back to its positive complement (same number 4 we started with). Show your work for full credit.
Feedback: 00000100 (4) 11111011 (flip bits) 11111100 (add binary 1, -4) 11111100 (-4) 11111011 (subtract binary 1) 00000100 (flip bits, 4)
Multiply the 2s complement numbers 0110 and 0111 using Booth's Algorithm with the step-by-step we learned in class. You'll need to extend 0110 to 8 bits and find its complement.
Feedback: 00000110 00000110 11111001 flip bits 11111010 add binary 1 (-6) 0110 (6) x 0111 (7) --------------------------- 1111 11111010 00000000 00000000 00000110 ---------------------------- 00100101010 xxx00101010 base 2 = 42 base 10
Multiply the following 4 bit unsigned integers using standard binary multiplication: 0010 and 0100.
Feedback: 0100 x0010 ---------- 0000 0100 0000 0000 ------------- 0001000
Evaluate the following instruction (MARIE architecture) to determine its human-readable opcode (example: LOAD) and the hexadecimal number (will be 3 hex characters) of the specified memory address: 0100000000011111
Feedback: 0100=SUBTRACT 0000 0001 1111 = 0 1 F = 1F SUBTRACT 1F
Write the numbers 98 and 35 in base 2 two's compliment. Add them together using binary arithmetic. Is the final answer correct? Why or why not?
Feedback: 11 1 01100010 (98) +00100011 (35) ----------------- 10000101 (-123) We had an overflow into the sign bit, and we arrived at an incorrect answer as a result.
Create a truth table for the following function: f(A,B,C) = B(A+C)
Feedback: A B C X 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1
If I needed a character code to store hundreds of thousands of symbols from languages all around the world, what would be a character code covered in class you would recommend? Explain two other benefits of your choice (other than number of code points).
Feedback: UTF-8 It has many code points, but also: - Can store the English alphabet in a single byte like ASCII - Compatible with ASCII for the first 128 characters - Resilience to corruption - Dynamic number of bytes per code point - And more!
In your own words, explain one problem discussed in class related to using signed magnitude integers.
Feedback: VS 2s compliment: - Math is more complicated when using negative numbers - Multiple values for zero cause issues when comparing VS Unsigned Integers -Signed magnitude can store half as many positive number as unsigned integers.
Convert .712 base 10 to base 5 using the division method. Show your work for full credit.
Feedback: .712*5=3.56 .56*5=2.8 .8*5=4 .324
An example of MARIE's 16 bit expanding opcodes is pictured. In MARIE's expanding opcode architecture, what is the most ideal number of operands we could reserve for the INPUT instruction (0-3 are the possible answers)? Why?
Feedback: 0. With an implied source (Input Register) and implied destination (Accumulator), we don't need to specify any operands. It is most efficient to have no operands and fill up a lower value 16 bit opcode.
Write decimal 3 and decimal 9 in base 2. Then, add them together using binary arithmetic. Show your work for full credit.
Feedback: 11 1001 (9) +0011 (3) -------------- 1100 (12)
Imagine a very simple stack architecture system where data can only be stored in a single stack. Explain the process for adding then removing two operands from the stack.
Feedback: Stacks act as first in, last out. You could use the PUSH instruction twice to add two operands to the stack. You could then use the POP instruction twice to remove the two operands.
Using MARIE's buses (Hint: great picture in the slides), the MBR and the AC are both connected to the ALU, but the ALU only connects back to the AC. Why?
Feedback: The ALU must take input from both the MBR and the AC for some instructions, like ADD or SUBTRACT, but the ALU always writes the output back to the AC - never the MBR.
Write the following function using the method discussed in class (hint: the out rows where you have 1): A B C X 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1
Feedback: f(A,B,C) = ABC' + AB'C + ABC It's the truth table for A(B+C).
Select the most true statement regarding hardware and software. A. Hardware and software are fully equivalent B. Hardware and software are equivalent, but software requires hardware C. Hardware and software are equivalent, but hardware requires software
Hardware and software are equivalent, but software requires hardware
Attached is a subset of MARIE's microprogram code in the control store. For the statement with address decimal 46 (convert to binary!), is the statement the first or last statement associated with the ADD instruction? What will be the address of the next statement to execute (you can use binary or decimal for your answer)? What is the name of the subroutine starting at that address?
It's the last statement for the ADD instruction - the actual adding of the MBR and AC together. The jump bit is set to 1, and the referenced address next to the jump bit is 0000000. The next step is to jump to 0000000 and restart the fetch-decode-execute cycle.
Convert 400 base 10 to base 8 using the division-remainder method. Show all your work for full credit.
400/8=50 remainder 0 50/8=6 remainder 2 6/8=0 remainder 6 620 base 8
Convert 45 in base 10 to base 2 using the subtraction method. Express your answer using a byte's worth of digits. Show all work for full credit.
45-32=13-8=5-4=1-1=0 00101101
I have a six input gate. How many rows exist in the gate's truth table (header not counted)?
64
When using a series of chained full adders (one pictured), the value of the carry in for the lowest order bit will be A. 0 B. 1 C. Unknown
A. 0
If I created an overflow condition by adding unsigned integer 0001 to the unsigned integer 1111, what value would my 4 bits store? A. 0000 B. 1111 C. 11111 D. 00000
A. 0000
Which of the following is the accurate "binary contents" representation of the instruction "ADD 104" in MARIE? (Hint: ADD is instruction 3) A. 0011000100000100 B. 0001000100000100 C. 0011000100000000 D. 0001000001000011
A. 0011000100000100
Which of the following 8 bit floating point numbers is normalized? A. 0|010|1101 B. 0|011|0100 C. 1|0100|010 D. 0|001|0101
A. 0|010|1101
In the non-superscalar Instruction pipelining example covered in class (and pictured), how many instructions does each stage operate on each cycle? A. 1 B. 2 C. 4 D. 3
A. 1
The 5 steps of the Fetch-Decode-Execute cycle are below. Which number is the Data Path cycle? 1. Fetch the next instruction from memory into the instruction register using the program counter, then increment program counter. 2. Decode the instruction. 3. Fetch data operands from memory into CPU registers. 4. The ALU executes the instruction and stores the result in registers or memory. A. 4 B. 3 C. 2 D. 1
A. 4
Which component of the Von Neumann machine is a small memory component and would in modern day probably be called a Register? A. Accumulator B. ALU C. Control Unit D. Main Memory
A. Accumulator
In MARIE's architecture, you may commonly see "IR[11-0]" and IR[15-12]" in the fetch execute decode cycle RTN. What exactly is stored in "IR[11-0]" and IR[15-12]"?
"IR[11-0]" will be the memory address specified in the instruction if one is required. "IR[15-12]" will be the opcode that must be decoded.
What is one reason why MARIE's microprogram statements have room for two microop codes? Why is the Jump bit only one bit in MARIE's microprogram statements?
- allowing an IF statement in MicroOp1 to compare to data in MicroOp2 - allow issuance of more than one microop code if both microop codes can be completed in a single clock cycle The Jump bit is only one bit because there are only two options: jump or don't jump. 1 bit can store both possible options.
Convert 110010101000000111 from binary to octal. Show your work for full credit.
1 100 101 010 000 001 111 1 4 5 2 0 1 7 1452017 base 8
A non-inverting buffer with a control line value of 0 and a data in of 1 will output A. Disconnect B. 1 C. Unknown D. 0
A. Disconnect
A modern Intel x86 processor is best classified as which architecture? A. General-Purpose Register Architecture B. Accumulator Architecture C. Stack Architecture
A. General-Purpose Register Architecture
The number of clock cycles from then an interrupt is generated to when the process routine starts is the A. Interrupt Latency B. Hardware Interrupt Clock Speed C. Hardware Interrupt Clock Time D. Software Interrupt Clock Time
A. Interrupt Latency
Which law could NOT help simplify the function f(A,B,C) = (ABC)(AB)? A. Inverse Law B. Distributive Law C. Idempotent Law
A. Inverse Law
Which of the following general-purpose register architecture types is most closely associated with RISC computers? A. Load-store B. Register-memory C. Memory-memory
A. Load-store
Which of the following is the least likely to be found inside a computer's CPU? A. Main Memory B. ALU C. Buses D. Registers E. Control Unit
A. Main Memory
The combinatorial circuit shown is a A. Multiplexer B. Decoder C. Comparator D. Demultiplexer
A. Multiplexer
The primary benefit of a clocked D flip-flop over a clocked SR latch is the ability to A. Prevent the metastable state B. Utilize an enable line to control when state can change C. Implement a clock to control the circuit
A. Prevent the metastable state
A hard drive would be best classified as which main computer component? A. Secondary Memory B. Processor C. Primary (Main) Memory D. Input/Output
A. Secondary memory
Splitting instructions and data is common in registers and CPU caches because... A. Simultaneous access to instructions and data is common B. Access to data needs to occur significantly faster than access to instructions C. Access to instructions needs to occur significantly faster than access to data
A. Simultaneous access to instructions and data is common
Which of the following CPU components is responsible for fetching and decoding instructions? A. The Control Unit B. The ALU C. The Instruction Register D. The Program Counter
A. The Control Unit
Decoding the instruction must always take place before an instruction is executed. A. True B. False
A. True
A CS value of 1, RD value of 0, and an OE value of 1 would cause what operation? A. Write B. Neither C. Read D. Both read and write
A. Write
If I wanted to quadruple a number, I could use A. a double left binary shift B. a right binary shift C. a left binary shift D. a double right binary shift
A. a double left binary shift
Copy the "chart" between the lines below into your answer box. Then, replace each "#" sign with a 0 or 1 such that the memory circuit will output (read) the values stored in Word Line 1. A0 - # A1 - # CS - # RD - # OE - #
A0 - 1 A1 - 0 CS - 1 RD - 1 OE - 1
Copy the "chart" between the lines below into your answer box. Then, replace each "#" sign with a 0 or 1 such that the memory circuit will output (read) the values stored in Word Line 1. A0 - A1 - CS - RD - OE -
A0 - 1 A1 - 0 CS - 1 RD - 1 OE - 1
I can write the output of a gate with inputs A and B as F(A,B)=AB. What is the name of the gate?
AND
When expressing a number in octal, the positional weight of the digit two to the left of the radix point (decimal point in base10) is... A. 8^0 B. 8^1 C. 8^3 D. 8^2
B. 8^1
The sample computer discussed in this class, MARIE, is most closely associated with which architecture type? A. Stack Architcture B. Accumulator Architecture C. General-Purpose Register Architecture
B. Accumulator Architecture
Hexadecimal numbers are best represented with how many bits per digit? A. 1 B. Hex does not translate into a consistent number of bits. C. 4 D. 3
B. Hex does not translate into a consistent number of bits.
A CS value of 0, RD value of 1, and an OE value of 1 would cause what operation? A. Write B. Neither C. Read D. Both and write
B. Neither
The JUMP instruction will change the value stored in which location? A. Instruction Register B. Program Counter C. The value specified in the JUMP instruction. D. Accumulator
B. Program Counter
The expanding opcode "1111 1100 1111 1111" would have how many available address codes according to the pictured opcode design? A. 4 B. 3 C. 2 D. 1
C. 2
The register transfer notation below could be used for what operation? MAR <- X MBR <- M[MAR] MAR <- MBR MBR <- M[MAR] AC <- AC + MBR A. STOREI B. LOADI X C. ADDI X D. JnS
C. ADDI X
Which of the following components of a bus is most likely to transmit the binary sequence for a memory location? A. Control Line B. Power Line C. Address Line D. Data Line
C. Address Line
Which of the following is an example of unconditional branching in MARIE's architecture? A. LOAD B. ADD C. JUMP D. SKIPCOND
C. JUMP
What instruction is represented by the register transfer notation below? MAR <-- X MBR <-- M[MAR] AC <-- MBR A. OUTPUT B. STORE C. LOAD D. SKIPCOND
C. LOAD
Which gates can be used to represent any other gate or circuit? (select many) A. AND B. NOT C. NOR D. OR E. NAND
C. NOR E. NAND
ISU pays many vendors to host and support applications on our behalf. Which of the following does this example best describe? A. Compute as a Service B. Platform as a Service C. Software as a Service D. Infrastructure as a Service
C. Software as a service
For a Radix n, how many unique symbols are needed to express a number? A. n+1 B. n-1 C. n D. 10
C. n
An address of 00 would select word line A. 3 B. 1 C. 2 D. 0
D. 0
Which of the following is an acceptable schema for a 16 bit signed floating bit number? A. 2 sign bits, 4 exponent bits, 10 significand bits B. 1 sign bit, 6 exponent bits, 10 significant bits C. 6 exponent bits, 10 significand bits D. 1 sign bit, 3 exponent bits, 12 significand bits
D. 1 sign bit, 3 exponent bits, 12 significand bits
The radix primarily used by humans for expressing numbers is A. 2 B. 16 C. 8 D. 10
D. 10
In MARIE, the indirect addressing instruction ADDI would contain a memory address in the instruction. What does the memory address point to in main memory? A. The next instruction B. A pointer to the next instruction C. The operand to be used in instruction execution D. A pointer to the operand to be used in instruction execution
D. A pointer to the operand to be used in instruction execution
What is the term for running two operands and an instruction through the ALU? A) Register-memory instructions B) Instruction register C) Register-register instructions D) Data Path Cycle
D. Data Path Cycle
If memory is 8 bits wide, changing from byte-addressed memory to word-addressed memory in a 16 bit word-length architecture will A. Quadruple the number of required addresses B. Divide the number of required addresses by 4 C. Double the number of required address D. Halve the number of required addresses
D. Halve the number of required addresses
Which of the following levels in a multilevel machine is the "true machine language" that can be run by hardware? A. Control/Microarchitecture Level B. OS/SS Level C. Digital Logic Level D. ISA/Machine Level
D. ISA/Machine Level
Which of the following would NOT be a result of the driving forces of Moore's Law? A. The newest generation of processors is faster than the last generation. B. I can buy today's computer for cheaper next year. C. Laptop memory can hold significantly more memory in the same RAM stick when compared to a decade ago. D. The newest graphics cards produce more heat than 5 years ago.
D. The newest graphics cards produce more heat than 5 years ago.
What gate is identical to a NOR gate with two inputs, A and A? A. NOR B. AND C. NAND D. OR E. NOT
E. NOT
I have a comparator circuit that validates whether the bits in two words are equal. What gate is most efficient at comparing if two inputs are equal? A. AND B. NOT C. NOR D. OR E. NAND F. XOR
F. XOR
A NAND gate has inputs A, B, and C. All inputs are high (1). The output of the gate will be high voltage (1). T or F
False
A powerful server is better than a disposable computer. True or False
False
Write 65 base 10 in unsigned binary. If I divided the unsigned binary number in half using a right binary shift, would I overflow? Would I get a perfectly correct answer?
Overflow cannot occur with a right arithmetic shift. However, we would be off by 1 on our answer. We'd lose a 1 bit in the least significant digit.
For the attached picture showing the control and bus lines connected to MARIE's MBR, fill in a "0", "1", or "does not matter" for each control line so that the MBR sends its current value to the bus. You should have "does not matter" as the answer for all control lines that control the register that will take the values from the bus during this clock cycle.
P0-1 P1-1 P2-0 P3-Does not matter P4-Does not matter P5-Does not matter
Is a reduced instruction set computer or a complex instruction set computer faster? Explain why a reduced instruction set computer requires more memory and registers than a complex instruction set computer.
RISC is faster. A RISC computer requires more memory than a CISC computer because a most tasks take significantly more instructions to complete on a RISC computer. More instructions means that comparably more memory and registers are needed to store and execute instructions.
As they pertain to ISA design decisions, explain one advantage of a short instruction, and explain one advantage of a long instruction.
Short instructions reduce system complexity and decode significantly faster. Long instructions allow more operands/addresses and allow for a more rich instruction set.
Which pictured component temporarily caches microinstructions before a microinstruction control word is issued to the rest of the CPU? What goal would a cache of microinstructions accomplish in a microprogrammed computer?
The Microinstruction Buffer caches microinstructions. A cache of ready microinstructions attempts to reduce the amount of stalling in the CPU. Micropragrammed control has a longer pipeline than hardware control and need to reduce stalling.
Explain the purpose of a bias in the exponent digits of a floating point number.
The bias allows us to split the number. The lower portion of the numbers below the bias are negative exponents, and the upper portion are positive exponents
If I were to double the binary 2s complement value for 85 base 10 (stored as 8 bits) with a left arithmetic shift, would I encounter any issues? Why?
The bit to the right of the sign bit would overflow into the sign bit.
Attached is a picture demonstrating part of MARIE's control matrix. Explain how the cycle counter connects to the pictured circuit. Which pictured control line resets the cycle counter?
The cycle counter connects into the pictures circuit using the T3-T5 lines. The T lines incrementally assert as microinstruction execution progresses (the connected AND gates) and the clock advances. Cr is control reset and resets the control line after the current instruction has finished executing.
Adding an enable line to make an SR flip-flop a clocked SR latch allows for more granularly controlling when the flip-flop can change states, such as with a clock. T or F
True
Interrupt processing takes priority over the execution of other programs even if multiple interrupts are queued. T or F
True
NOT, NAND, and NOR gates will all output high voltage (1) when all of their input voltages are low (0). T or F
True
The Program Counter keeps track of the next instruction to be fetched. True False
True
The program counter (PC) and instruction register are both responsible for keeping track of program execution sequence. T or F
True
With floating point numbers, we have a range of numbers we can store. However, it is possible to have numbers in the range that cannot be stored with perfect accuracy. Why?
We have limited precision with floating point numbers, and we may have to accept a number merely close to the number we actually want. "Close enough."
Write the number 7 as a normalized floating point number using 12 bits with a 6 bit significand and a 15 bit exponent bias. Show your work.
convert decimal to binary: 710 = 000001112 00000111 = 0.111 x 23 add the bias .0111 x 218 sign exponent significand 0 10010 111000
