Quiz 3 Cse 3666

The simple implementation of a RISC-V ALU subset covers the following instructions:

- Load(lw) / Store(sw) --> F = add ( add because you add the offset to adress to find effective address) - Branch (beq) --> F = subtract (subtract because you subtract the values to see if it equals 0, because if it does they're the same) - R-type --> F depends on the opcode function field (it can be add, subtract, and , or OR)

Combinational elements(e.g. AND, ALU)

- Operate on data - Output is a function of input

Describes the steps to executing a Load/store instruction:

- The instruction is fetched from I-mem using the address in PC - Register is read from the register file (RF) - ALU computes the address - The data is read or written in memory - in a load instruction the data is also written into RF

what is elapsed time?

- Total response time including all aspects (Processing, I/O, OS overhead, idle time) - determines system performance

What are the timing requirements for a D-flip flop?

- setup time - hold time - propagation delay

Describes the steps to executing a branch instruction:

- the instruction is fetched from I-mem using the address in PC - The 2 registers are read from the RF - The ALU compares the contents in the 2 registers - The PC is updated

What component should be used to select the specific register to write?

-A decoder (Register number goes into a decoder, which activates one only register) -Register Data are sent to all registers

Describe the steps to executing an ADD instruction:

-ADD instruction is fetched from I-Mem, using the address in PC -Register rs1 and rs2 are read from the Register File (RF) - ALU performs addition on the contents of rs1 and rs2 -The result is saved into register rd in the RF

information encoded in binary :

-Low voltage = 0 -High voltage = 1 - One wire per bit - Multi-bit data encoded on multi-wire buses

How is performance improved?

-Reducing number of clock cycles -increasing clock rate -Reducing the clock cycle time

what happens if an instruction does write to a register?

-Set write register and write data -Set Write to 1 -Wait for clock to change

what does an immediate data generator do?

-Takes a 32-bit instruction as input; -Extracts the 12-bit immediate data; - Extends it to 32 bit

when is the register with write control updated with D ?

-The register is updated with D on clock edge only when write control input is 1

What is CPU time?

-Time spent processing a given job -Comprises user CPU time and system CPU time -Different programs are affected differently by CPU and system performance

How to build a datapath for a BEQ instruction?

-beq x1, x2, offset -Read register operands - Compare operands -Use ALU, subtract and check Zero output -target address - Sign-extend displacement - Shift left 1 place (halfword displacement) - Add to PC value

The funct 7 for AND and OR is _____

0000000

what is the ALU op for beq

01

what is the ALU op for R-type

10

The funct3 for AND and OR is:

111; 110

Risc-v Registers file has _____ write port

1;

ALu control uses ___ bit ALUop instead of ________ directly

2-bit; opcode

10s * 2 GHz =

20 * 10^-9

Risc- V Register file (RF) has ____ read ports and can read ______ registers at a time

2; 2;

Program counter is ___ bit register

32

Risc-v has _____ registers

32, 32-bit registers

what determines when to update the data in a D flip-flop?

A clock signal determines when to update the data; updates happen when the clock changes from 0 to 1

A storage element in a digital circuit can maintain _______ indefinitely, until __________

A storage element in a digital circuit can maintain a binary state indefinitely (as long as power is delivered to the circuit), until directed by an input signal to switch states

Synchronous

A synchronous sequential circuit is a system whose behavior can be defined from the knowledge of its signals at discrete instants of time.

Asynchronous

An asynchronous sequential circuit depends upon the input signals at any instant of time and the order in which the inputs change.

As CPU execution time ________, performance __________

As CPu execution time increases, performance decreases

clock period is also known as:

Clock cycle time

What does ALU do for an Branch instruction?

Compares

What does ALU do for an load/store instruction?

Computes address

What does ALU do for an R-type instruction?

Computes result

In a +edge triggered flip flop, D_____ but does not ______ Q

D changes, but does not change Q

Data stored in _____ are _____ until next trigger

Data stored in registers are steady until next trigger

What is the effect when the RegWrite signal is deasserted vs asserted?

Deasserted: none Asserted: The register on the write register input is written with the value on the write data input

what is another name for the write signal?

Enable

What is response time ?

How long it takes to complete a task

What component can we use to control decisions and avoid joining wires together in a CPU?

MUXES!

Does every instruction take the same number of cycles to execute

NO, Instructions take different number of cycles to execute Example: One cycle for add, 10 cycles for mul, 20 cycles for lw The same instruction may take different numbers of cycles --> CPU Hardware

What is CPU clocking?

Operation of digital hardware governed by a constant-rate clock -( data transfer and computation is done in one clock period, and is updated at the rising edge of the clock period, or the ned of a clock period).

Combinational Circuits

Outputs at any time are determined from only the present combination of inputs

Sequential circuits

Outputs depend upon both the present and past inputs.

What are two types of digital circuits

Sequential and combinational circuits

latches

Storage elements that operate with signal levels (rather than signal transitions) (level sensitive devices)

what do synchronous sequential circuits look like ?

Synchronous sequential circuits look just like a standard sequential circuit except it has an input to the memory component (clock pulses)

Clocked sequential circuits

Synchronous sequential circuits that use clock pulses to control storage elements

what defines the state of a sequential circuit ?

The binary information stored in memory elements at any given time defines the state of the sequential circuit at that time.

What component is used to calulate offset for lw/sw instructions and how many bits is it?

The immediate generator (imm gen) is used and it uses a 12 bit immediate

the next state of the storage elements is a function of ___

The next state of the storage elements is also a function of external inputs and the present state.

what are the outputs in a sequential circuit a function of

The outputs in a sequential circuit are a function not only of the inputs, but also of the present state of the storage elements.

Why do datapaths need separate instruction and data memories?

The processor operates in one cycle and cannot use a (singleported) memory for two different accesses within that cycle

In a +edge triggered flip flop, when is the value of D stored?

The value of D at the rising edge of the control (clk/clock) is stored

What is propagation delay for a D flip flop?

Time for input to propagate to output ( the space between clock edge and Q edge) (also is after the clock edge, not before since it is propagating an output)

How is ALU operation generated?

We could generate it directly from opcode, funct3, and funct7 The main control checks opcode (and opcode only) and generates a 2-bit signal ALUOp that indicates the instruction type

Register

a memory element that stores data and can be a flip flop, or other kinds of flip- flops

What type of instruction is R-type and what is the opcode for R-type instructions?

add, subtract, and, or; 011 0011

What type of instruction is an SB-type and what is it's opcode?

beq; 110 0011

how is synchronization achieved?

by a timing device called a clock generator, which provides a clock signal having the form of a periodic train of clock pulses.

what is clock signal usually denoted by?

clk or clock

what is CPI

cycles per instruction

Clock frequency / rate

cycles per second

What is the effect when the PcSrc signal is deasserted vs asserted?

deasserted: The PC is replaced by the output of the adder that compted the value of PC + 4 asserted: The PC is replaced by the output of the adder that computes the branch target

What is the effect when the AluSrc signal is deasserted vs asserted?

deasserted: The second ALU operand comes from the comes from the second register file output (read data 2) Asserted: The second ALU operand is the sign-extended 12 bits of the instruction

Clock period :

duration of a clock cycle

How many functions can each datapath element do at a time? (eg. RF and ALU)

each datapath example can only do one function at a time, and they cannot be used twice- therefore we need separate instruction and data memories.

What is a datapath?

elements that process data and addresses in the CPU For example (Registers, ALUs, MUXes, memories, ...)

how do you determine how much faster processor A is than processor B?

execution time(b) / execution time (a)

What is setup time for a D flip flop?

has to be ready before the clock edge

What is hold time for a D flip flop?

has to hold steady for some time after the edge

a clock signal oscillates between ____ and _____ values

high; low;

How do you select a specific register to read or write?

incorporate 2 muxes for two read ports(the muxes will both connect to the registers file and will each read a register).

Data memory can only be accessed by a ______ instruction

load/store

What type of instruction is an I-type and what is it's opcode?

lw; 000 0011

Use _____ where alternate data sources are used for different instructions

multiplexors

if the operands are equal in a beq instruction, the branch target address= _____, if the branch is not taken _______. IF branch is not taken, ___

new PC; Pc= pc + 4

what is one of the units for clock cycle time ?

ns

CPU time =

number of clock cycles * Clock cycle time OR number of clock cycles/Clock Rate

each instruction is executed in:

one clock period / cycle

What are the two inputs for a memory instruction

one input from register and one input from 12- bit offset

We can define performance as :

performance = 1/ CPU time

The clock rate/ frequency is the :

reciprocal of the cycle time that can be defined by frequency = 1/ clock cycle time

what happens if an instruction does not write to a register ?

set write signal to 0

What type of instruction is an S-type and what is it's opcode?

sw; 010 0011

clock period

the time for one full cycle

Flip Flop

(Edge sensitive devices) that are controlled by a clock transition

What are the different ways of measuring time?

- Elasped time - CPU time

State (sequential) elements (e.g. Registers, Memory)

- Store information - Operate on at least two inputs - input data, clock

What happens if an instruction needs to read a register?

-Set read register numbers -Wait for data to be ready

Throughput

-Total work done per unit time -example (e.g., tasks/transactions/... per hour)

what is the ALU op for lw and sw

00

Add and subtract have funct 3 and funct 7 ____

000; 0000000;

what is the unit for clockrate/frequency ?

GHz

Datapath can execute an instruction in _____

One clock cycle

What does data memory do for a branch instruction:

Updates PC; (Does not use data memory)

to store a bit in D flip-flop, _________

to store a bit in D flip-flop, set up D and make C transit from 0 to 1

what happens when the write signal control input is 0?

you keep the original value in the register Often