CS 311 - Test 3

Examples of Cluster Computing

PoPCs, DCPC, NOWs, COWs

4 Types of Architecture Classifications

SISD, SIMD, MISD, & MIMD

Vector Processors

often referred to as supercomputers, are specialized, heavily pipelined SIMD processors that perform vector operations on entire vectors and metrics at once

Output Registers

overlap with the next windows input register

Input Registers

overlap with the preceding window's output register

Non Preemptive Scheduling

process has use of the CPU until either it terminates, or must wait for resources that are temporarily unavailable

Binding

process of assigning physical addresses to program variables can occur at compile time, run time, or load time

Vector Computers

processors that operate on entire vectors or matrices at once. often called supercomputers

Virtual Machines

protected environment that presents an image of itself, or the image of a totally different architecture, to the process thats run within the environment

Subsystems

provide logically distinct environments that can individually controlled and managed. They can be stopped and started independent on each other

Microkernel Systems

provide minimal functionality, with most services carried out by external programs provide better security, easier maintenance, and portability at the expense of execution speed

Monolithic Systems

provide most of their services within a single operating system program give faster execution speed, but are difficult to port from one architecture to another

4 CPU Scheduling algorithms

round-robin, priority, sjf, fcfs

Priority

scheduling preempts a job with a lower-priority when a higher-priority job needs the cpu

Round-Robin

scheduling where each job is allowed a certain amount of CPU time. A context switch occurs when the time expires

Distributed Computing

set of networked computers that work collaboratively to solve a problem

Cluster of Workstations (COWs)

similar to NOW, but requires a single entity to be in charge

Bus-Based Networks

simplest and most efficient dynamic network allowing a moderate number of entities when cost is of concern

VLIW

simplifies the hardware by relying entirely on the compiler for approximate scheduling

SIMD

single instruction stream, multiple data streams single point of control, execute the same instruction simultaneously on multiple data values

SISD

single instruction stream, single data stream uniprocessors

Thread

smallest schedule unit in a system

System Software

software which directly operates the hardware and provide a platform to enable the running of application software

Application Software

software which is designed to accomplish a task or perform a special function or provide entertainment by using a computer system

Crossbar Switches

switches that are either open or closed

2 Major Parallel Architectures

symmetric multiprocessors (SMPs) & massively parallel processors (MPPs) both MIMD

Soft Real-Time Operating Systems

systems do not have tight timing constraints for response

Compiler

takes as input a high-level language source code and translates to equivalent object program as output

Interrupt Latency

the elapsed time between the occurrence of an interrupt and the execution of the first instruction of the interrupt service routine (ISR)

Assemblers

the simplest of all programming tools and translate mnemonic instructions to machine code most carried out the translation in two passes over the source code

Message Latency

time required for the first bit of a message to reach its destination

Transport Latency

time the message spends in the network

Switching Networks

use switches to dynamically alter routing

Static Networks

used mainly for message passing

Memory-Memory

vector processors allow operands to be sent from memory directly to the arithmetic units Disadvantage: have a longer startup time until the pipeline becomes full

Register-Register

vector processors require all operands to be in registers Disadvantage: large vectors must be broken into fixed length segments so they will fit into the register sets

3 Common Environments to Establish Protected Environments

virtual machines, subsystems, partitions

Context Switch

when running process needs an I/O or other resources, it voluntary relinquishes the CPU and places itself in waiting list, and another process is scheduled for execution

FCFS

where jobs are serviced in arrival sequence and run to completion if they have all of the resources they need

SJF

where the smallest jobs get scheduled first. (trouble is knowing which jobs are shortest)

Bus-Based Network

while economical, can be bottlenecks. Parallel buses can alleviate bottlenecks, but are costly

Programmable Logic Array (PLA)

chips that consist of programmable AND gates connected through programmable OR gates

Programmable Array Logic (PAL)

chips that consist of programmable AND gates connected to a set of fixed OR gates

Flynn's Taxonomy

classification of computer architectures that considers the number of instructions and the number of data streams that flow into the processor

Pile of PCs (PoPC)

cluster of dedicated heterogeneous hardware used to build a parallel system out of a mass market commodity components

Network of Workstations (NOWs)

collection of distributed workstations that work in parallel only while the nodes are not being used as regular workstations

Dedicated Cluster Parallel Computer (DCPC)

collection of workstations specifically collected to work on a given parallel computation

Global Registers

common to all windows

Programmable Logical Devices (PLDs)

configurable devices in which the behavior of the circuits can be changed to suit the needs of an application

Real-Time Operating Systems

control computers that respond to their environment

Field Programmable Gate Array (FPGA)

controlled through the values stored in memory lookup tables rather than by changing connections between logic elements

Kernel

core of the operating system that performs scheduling, synchronization, memory management, interrupt handling, and it provides security and detection

Two Types of Switches

crossbar and 2x2 switches

Superscalar Architecture

design methodology that allows multiple instructions to be executed simultaneously in each cycle achieve speedup by "adding more lanes (hardware execution units) for the cars to drive on"

Cluster Computing

distributed computing in which the resources are all within the same administrative domain

Preemptive Scheduling

each process is allocated a timeslice. When the timeslice expires, a context switch occurs

Single Program Multiple Data (SPMD)

extension to Flynn's Taxonomy that consists of multiple processors, each with its own data set and program memory

Symmetric Multiprocessors (SMP)

few processors + shared memory + communication via memory suffer from serious bottleneck when simultaneous memory access occurs

Hard Real-Time Operating Systems

have tight timing constraints for response

Bandwidth

information carrying capacity of the network

Local Registers

local to the current window

Massively Parallel Processors (MPP)

many processors + distributed memory + communication via network more complex to program bc CPU communication use if problem is easily partitioned (data mining)

Overhead

message-processing activities in the sender and the reciever

Multistage Interconnection Networks

most advanced class of networks that incorporates a stage of switches, typically with processors on one side and memory on the other, with a series of switching elements as the interior nodes. can allow a path from any different processor to any different memory with dynamic switching often called shuffle networks

MIMD

multiple instruction streams, multiple data streams employ multiple control points and have independent instruction and data streams (multiprocessors)

MISD

multiple instruction streams, single data stream employ multiple control points and have same data streams

Loosely Coupled

multiprocessor systems have physically separate memory

Tightly Coupled

multiprocessor systems share a common memory and the same set of I/O devices

Linear Array or Ring Network

network that allows any entity to directly communicate with its two neighbors, but requires any other communication to go through multiple entities

Tree Network

network that arranges entities in noncyclic structures, which have potential for communication bottleneck at its roots

Completely-Connected Networks

network that each component are connected to all other components

Star-Connected Networks

network that has a central hub through which all messages must pass through

Hypercube Networks

network that is a multidimensional extension of a mesh network in which each dimension has two processors

Mesh Network

network that links any entity to four or six neighbors depending on the network dimension

Crossbar Networks

nonblocking, but require n^2 switches to connect n entities

Superpipelining

occurs when a pipeline has stages that requires less than half a clock cycle to execute

2x2 Switches

a switch with 2 inputs and 2 outputs, capable of routing inputs to different destinations can be in 1 of 4 stages: through, cross, upper broadcast, & lower broadcast

Dynamic Networks

allow the path b/w two entities to change from one communication to the next

Multithreading

allowing a process to be subdivided into different threads of control

Multitasking

allowing multiple processes to run concurrently

Omega Networks

blocking networks, but exhibit less contention than bus-based networks. They are somewhat more economical than crossbar networks, n nodes needing log2 n stages with n/2 switches per stage