PLTW Digital Electronics - Final Review Set 1, PLTW Digital Electronics - Final Review Set 2, PLTW Digital Electronics - Final Review Set 3, Digital Electronics - PLTW Review Test

Edge-Sensitive

Manner in which a flip-flop is activated by a signal transition. A flip-flop may be either a positive-or a negative-edge-triggered flip-flop

What is the binary equivalent to the hexadecimal number CH

11002

What is the binary equivalent to the decimal number 1310?

1101

How many flip-flops are required to implement a divide-by-4 circuit? 1. 4 2. 3 3. 2 4. 1

2

What is the decimal equivalent to the binary number 0101102?

22 base 10

What is the decimal equivalent to the binary number 0101102?

22 power of 10

What is the minimum number of flip-flops needed to build a Mod-10 Asynchronous counter? 1. 32 2. 64 3. 4 4. 10

4

What is the value of the resistor with colors blue, grey, red , gold ?

6.8 K Ω ±5 %

In a parallel circuit, you measure 1.5 mAmps flowing through a 600 Ω resistor. What is the voltage drop across the resistor? Use Ohms law.

900 m Volts

Simple PLD (SPLD)

A PLD with a few hundred logic gates and possibly a few programmable macro cells available.

De-multiplexer (DEMUX)

A circuit that uses a binary decoder to direct a digital signal from a single source to one of several destinations.

Design Specifications

A detailed description, especially one providing information needed to make, build, or produce something.

Encoder

A digital circuit that produces an output code depending on which of its inputs is activated.

Complex PLD (CPLD)

A digital device consisting of several programmable sections with internal interconnections between the sections.

Datasheet

A printed specification giving details of the pin configuration, electrical properties, and mechanical profile of an electronic device.

Flip-Flop

A sequential circuit based on a latch whose output changes when its CLOCK input receives a pulse

State Machines

A sequential circuit that advances through several defined states

Common Anode Display

A seven-segment LED display where the anodes of all the LEDs are connected to the circuit supply voltage. Each segment is illuminated by a logic LOW at its cathode.

Common Cathode Display

A seven-segment display in which the cathodes of all the LEDs are connected together and grounded. A logic HIGH illuminates a segment when applied to its anode.

Schematic Entry

A technique of entering CPLD design information by using a CAD (computer aided design) tool to draw a logic circuit as a schematic. The schematic can then be interpreted by design software to generate programming information for the CPLD.

Which of the following is a rule of Boolean algebra? 1. AA • 0 = A 2. AB • 1= 1 3. A • A = A 4. AC • A = 1

A • A = A

Integrated Circuit (IC)

An electronic circuit having many components, such as transistors, diodes, resistors, and capacitors, in a single package.

Fitting

Assigning internal PLD circuitry, and input and output pins, to a PLD design.

Which of the following statements applies to asynchronous counters? 1. Asynchronous counters are faster than synchronous counters. 2. Asynchronous counters require more power than synchronous counters. 3. All the flip-flops in an Asynchronous counter are clocked at the same time by a common external clock. 4. Asynchronous counters are also called ripple counters.

Asynchronous counters are also called ripple counters.

RESET / CLEAR

Asynchronous input used to set Q=0 immediately

PRESET

Asynchronous input used to set Q=1 immediately

In the eight-bit binary number shown below, which bit is the Least Significant Bit (LSB)? b7b6 b5 b4 b3 b2 b1 b0 1 0 1 1 0 1 0 1

B 0 (zero)

D Latch

Circuit that contains a NAND gate latch and two steering NAND gates

Synchronous Counter

Counter in which all of the flip-flops are clocked simultaneously

Propagation Delays (tPLH/tPHL)

Delay from a time signal is applied to the time when the output makes its change

Sequential Logic

Digital circuitry in which the output state of the circuit depends not only on the states of the inputs, but also on the sequence in which they reached their present states

Shift Register

Digital circuitry that accepts binary data from some input source and then shifts these data through a chain of flip-flops one bit at a time

Programmable Logic Device (PLD)

Digital integrated circuit that can be programmed by the user to implement any digital logic function.

Clock

Digital signal in the form of a rectangular pulse train or a square wave

Level-Sensitive

Enabled by a logic HIGH or LOW level

Which Boolean equation is in Product-Of-Sums form? 1. F = X Y Z + X Y + X Y Z 2. F = X Y Z + Z (X + Y) 3. F = (X + Y)(X+ Z)(Y + Z) 4. F = X Z(Y + Z)(Y + Z)

F = (X + Y)(X+ Z)(Y + Z)

Which of the following Boolean equation is in Sum-Of-Products form? 1. F = A B' C + A B C + A 2. F = (A')(B')(BC)(ABC) 3. F = (10010)11101001) 4. F = A' (B + C) A (B' + C)

F = A B' C + A B C + A

Which of the following equations is the un-simplified Sum-Of-Products equation for the truth table shown below with F as the Output? X Y Z F 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 0

F = X' Y' Z + X' Y Z' + X Y Z'

Asynchronous Inputs

Flip-flop inputs that can affect the operation of the flip-flop independent of the synchronous and clock inputs

Duty Cycle (DC)

Fraction of the total period that a digital waveform is in the HIGH state. DC = th/T (often expressed as a percentage: %DC = th/Tx100%)

What is the letter symbol for current?

I

Trigger

Input signal to a flip-flop or one-shot that causes the output to change states depending on the conditions of the control signals

Name the type of gate that is off when it is switched to the on position 1. And 2. Nand 3. Or 4. Inverter

Inverter

Name three processes for simplifying circuits 1.Boolean Algebra, Boolean Equations, Karnaugh maps 2.Boolean Geometry, Demorgans Theroem, Break the bar change the sign 3.Karnaugh Mapping, Demorgans Theorem, Boolean algebra 4.Simplify terms, karnaugh mapping, looping like terms

Karnaugh Mapping, Demorgans Theorem, Boolean algebra

Full Adder

Logic circuit with three inputs and two outputs. The inputs are a carry bit (CIN) from a previous stage, a bit from the augend, and a bit from the addend, respectively. The outputs are the sum bit and the carry-out bit (COUT) produced by the addition of the bit from the addend with the bit from the augend and CIN.

Half Adder

Logic circuit with two inputs and two outputs. The inputs are a bit from the augend and a bit from the addend. The outputs are the sum bit produced by the addition of the bit from the addend with the bit from the augend and the resulting carry (COUT) bit, which will be added to the next stage.

In scientific notation, which prefixes are used for values smaller than a whole value?

Micro, nano, milli

What type of gates can be used to replace an AOI circuit to make it smaller? 1. Exclusive OR/NOR 2. OR/AND 3. Inverter/NAND 4. NAND/NOR

NAND/NOR

What are the color bands for a 390 Ω (±10) resistor?

ORANGE-WHITE-BROWN-SILVER

How are the Q and Q' outputs of a flip flop affected by setting the active low asynchronous RESET input to a logic zero? 1. Q = 1 and Q' = 0 2. Q = 0 and Q' =1 3. invalid 4. No change.

Q = 0 and Q' =1

Period

The amount of time required for one complete cycle of a periodic event or waveform

Frequency

The number of cycles per unit time of a periodic waveform

Falling Edge

The part of a pulse where the logic level is in transition from a HIGH to a LOW

Rising Edge

The part of a pulse where the logic level is in transition from a LOW to a HIGH

JTAG Port

The port on the FPGA (CMOD) that data is received through when downloading a circuit.

Design Entry

The process of using software tools to describe the design requirements of a PLD. Design entry can be done by entering a schematic or a text file that describes the required digital function.

Compiler

The process used by CPLD design software to interpret design information (such as a schematic or text file) and create required programming information for a CPLD.

Target Device

The specific PLD for which a digital design is intended.

Propagation delay is _________________________. 1. A measure of the ability of a logic gate to drive further logic gates. 2. The difference in chip temperature from when the power is off to when the power is on. 3. The difference between what a logic gate outputs as a valid logic voltage and what the input of the next gates expects to see as a valid logic voltage. 4. The time required for a signal to travel from the input of a logic gate to the output.

The time required for a signal to travel from the input of a logic gate to the output.

Programming

Transferring design information from the computer running PLD design software to the actual PLD chip.

If an integrated circuit has been damaged and you smell smoke, you should__________________.

Turn the power off for a few minutes before pulling out the damaged integrated circuit.

Exclusive-OR (XOR) Circuit

Two-input logic circuit that produces a high output only when the inputs are different.

Exclusive-NOR (XNOR) Circuit

Two-input logic circuit that produces a high output only when the inputs are equal.

Asynchronous Counter

Type of counter in which each flip-flop output serves as the clock input signal for the next flip-flop in the chain

Clocked D Flip-Flop

Type of flip-flop in which the D (data) input is the synchronous input

Clocked J-K Flip-Flop

Type of flip-flop in which the inputs J and K are the synchronous inputs

Which of the following is a correct DeMorgan's Identity? 1.. XY" = X'•Y' 2. XY" = X'•Y 3. XY" = X' + Y' 4. XY = X + Y

XY" = X' + Y'

When comparing a PLD circuit to a logic circuit implemented with individual logic gates, the PLD circuit will ____________. 1. be easier to breadboard with fewer chips and wires. 2. require more chips and wiring. 3. require you to simplify the expression using a K-Map. 4.require a higher operating voltage.

be easier to breadboard with fewer chips and wires.

Field Programmable Gate Array (FPGA)

Class of PLDs that contain an array of more complex logic cells that can be very flexibly interconnected to implement high-level logic circuits.

. Which of the following is the simplified equivalent for the Boolean equation shown? F = Y' +XY' 1. F = X ''Y'' 2. F = X 3. F = X Y' 4. F = Y'

F = Y'