TTK4155 - Eksamensforberedelse

I2C-bus terminology Multi-master

more than one master can attempt to control the bus at the same time without corrupting the message

Features with 802.11b?

"Wifi" High power consumption Good range High data transfer rate High complexity

Explain the difference between polling and interrupt. When would you use what?

- Polling: Checks an input every iteration of the code. Works best when checking signals that are synchrounous, not so important and frequent - Interrupt: Triggers everytime a signal is detected, pauses the program and runs a special set of commands. Works best for signals that are asynchronous, urgent and infrequent.

Compare RAM, Flash and EEPROM

- RAM: Volatile, fast - Flash: Non-volatile, slower than RAM, high memory capacity, split into indifidual re-writable sectors - EEPROM: Non-volatile, slow, small memory capacity, everything must be erased when writing new information

Name some types of AD Converters

- SAR (successive approximation) ADC - Flash ADC - Integrating ADC (also dual-slope or multi-slope ADC

Name some types of DA Converters

- String DAC (Kelvin Devider) - R-2R ladder DAC - Simple PWM DAC

ZigBee devices are of three types

- ZigBee Coordinator (ZC): The most capable device, the Coordinator forms the root of the network tree. - ZigBee Router (ZR): As well as running an application function, a Router can act as an intermediate router, passing on data from other devices. - ZigBee End Device (ZED): Contains just enough functionality to talk to the parent node (either the Coordinator or a Router); it cannot relay data from other devices.

Name three microprocessor architectures

1. Von Neumann 2. Harvard 3. Digital Signal Processor (DSP)

The thermal shutdown, current limiter, and voltage error amplifier make up three distinct and separate control loops that have a definite hierarchy (pecking order) which allows one to "override" the other. The order of command (and importance) of the loops is:

1) Thermal Limit (IC is regulating junction temperature/power dissipation) 2) Current Limit (IC is regulating load current) 3) Voltage Control (IC is regulating output voltage) This hierarchy means that a linear regulator will normally try to operate in "constant voltage" mode, where the voltage error amplifier is regulating the output voltage to a fixed value. However, this assumes that both the load current and junction temperature are below their limit threshold values.

Name sources of static errors in ADC

1. Gain error 2. Offset error 3. Integral nonlineraity 4. Differential nonlinearity

What wires are needed for a SPI-com with one master and two slaves?

1. MOSI 2. MISO 3. SCLK 4. 2x Slave Select (SS)

What is the maximum length of a CAN-bus?

1000 meters

Explain what EPROM is

A (slightly) better choice for system development and debugging is the Erasable Programmable Read-Only Memory, or EPROM. Shining ultraviolet light through a small window on the top of the chip can erase the EPROM, allowing it to be reprogrammed and reused. They are pin- and signal-compatible with comparable OTP and mask devices. Thus, an EPROM can be used during development, while OTPs can be used in production with no change to the rest of the system. EPROMs and their equivalent OTP cousins range in capacity from a few kilobytes (exceedingly rare these days) to a megabyte or more. The drawback with EPROM technology is that the chip must be removed from the circuit to be erased, and the erasure can take many minutes to complete. The chip is then inserted into the burner, loaded with software, and then placed back in-circuit. This can lead to very slow debug cycles. Further, it makes the device useless for storing changeable system parameters. EPROMs are relatively rare these days. You can still buy them, but flash-based memory (to be discussed shortly) is far more common and is the medium of choice.

Balanced Line Receivers

A balanced differential line receiver senses the voltage state of the transmission line across two signal input lines, A and B. It will also have a signal ground (C) that is necessary in making the proper interface connection. Figure 1.3 is a schematic symbol for a balanced differential line receiver. Figure 1.3 also shows the voltages that are important to the balanced line receiver. If the differential input voltage Vab is greater than +200 mV the receiver will have a specific logic state on its output terminal. If the input voltage is reversed to less than -200 mV the receiver will create the opposite logic state on its output terminal. The input voltages that a balanced line receiver must sense are shown in Figure 1.3. The 200 mV to 6 V range is required to allow for attenuation on the transmission line.

What is the maximum CAN-bus length at maximum data rate over twisted -pair wiring?

A bus length of 40 meters (133 feet) at maximum data rate over twisted-pair wiring.

DSP

A digital signal processor (DSP) is a specialized microprocessor (or a SIP block), with its architecture optimized for the operational needs of digital signal processing. The goal of DSPs is usually to measure, filter and/or compress continuous real-world analog signals. Most general-purpose microprocessors can also execute digital signal processing algorithms successfully, but dedicated DSPs usually have better power efficiency thus they are more suitable in portable devices such as mobile phones because of power consumption constraints.[3] DSPs often use special memory architectures that are able to fetch multiple data and/or instructions at the same time.

What voltage range does the High and Low signals lie in for the RS-232C?

A logic high for RS-232C is a signal voltage in the range of -5 to -15 V (typically -12 V), and a logic low is between +5 and +15 V (typically +12 V). So, just to make that clear, an RS-232C high is a negative voltage, and a low is a positive voltage, unlike the rest of your computer's logic.

Why is the UART termed asynchronous?

They are termed asynchronous because no clock is transmitted with the serial data. The receiver must lock onto the data and detect individual bits without the luxury of a clock for synchronization.

What is a USB descriptor, describe them?

All USB devices have a hierarchy of descriptors which describe to the host information such as what the device is, who makes it, what version of USB it supports, how many ways it can be configured, the number of endpoints and their types etc The more common USB descriptors are : Configuration Descriptors: A USB device can have several different configurations although the majority of devices are simple and only have one. The configuration descriptor specifies how the device is powered, what the maximum power consumption is, the number of interfaces it has. Therefore it is possible to have two configurations, one for when the device is bus powered and another when it is mains powered. As this is a "header" to the Interface descriptors, its also feasible to have one configuration using a different transfer mode to that of another configuration. Interface Descriptors: The interface descriptor could be seen as a header or grouping of the endpoints into a functional group performing a single feature of the device. Endpoint Descriptors: Endpoint descriptors are used to describe endpoints other than endpoint zero. Endpoint zero is always assumed to be a control endpoint and is configured before any descriptors are even requested. The host will use the information returned from these descriptors to determine the bandwidth requirements of the bus. String Descriptors: String descriptors provide human readable information and are optional. If they are not used, any string index fields of descriptors must be set to zero indicating there is no string descriptor available.

Explain Acknowledgment (CAN):

All receivers check the consistency of the message being received and will acknowledge a consistent message and flag an inconsistent message.

Draw a RS-232C link

An RS-232C link consists of a driver and a comparator, as shown in Figure 9-3.

Boost regulator Output current and load power

An important design consideration in the Boost regulator is that the output load current and the switch current are not equal, and the maximum available load current is always less than the current rating of the switch transistor. It should be noted that the maximum total power available for conversion in any regulator is equal to the input voltage multiplied times the maximum average input current (which is less than the current rating of the switch transistor). Since the output voltage of the Boost is higher than the input voltage, it follows that the output current must be lower than the input current.

What is the purpose of vectored interrupts?

An interrupt vector is the memory location of an interrupt handler, which prioritizes interrupts and saves them in a queue if more than one interrupt is waiting to be handled.

Flyback regulator Generating multiple outputs

Another big advantage of a Flyback is the capability of providing multiple outputs (see Figure 34). In such applications, one of the outputs (usually the highest current) is selected to provide PWM feedback to the control loop, which means this output is directly regulated. The other secondary winding(s) are indirectly regulated, as their pulse widths will follow the regulated winding. The load regulation on the unregulated secondaries is not great (typically 5 - 10%), but is adequate for many applications. If tighter regulation is needed on the lower current secondaries, an LDO post-regulator is an excellent solution. The secondary voltage is set about 1V above the desired output voltage, and the LDO provides excellent output regulation with very little loss of efficiency.

Definition of Embedded computer system

Any device that contains a programmable computer which introduce some degree of intelligence to the system, but which itself is not a general purpose computer (such as PCs, workstations, laptops, tablets)

Tristate Control of an RS-485 Device using RTS

As discussed previously, an RS-485 system must have a driver that can be disconnected from the transmission line when a particular node is not transmitting. In an RS-232 to RS-485 converter or an RS-485 serial card, this may be implemented using the RTS control signal from an asynchronous serial port to enable the RS-485 driver. The RTS line is connected to the RS-485 driver enable such that setting the RTS line to a high (logic 1) state enables the RS-485 driver. Setting the RTS line low (logic 0) puts the driver into the tristate condition. This in effect disconnects the driver from the bus, allowing other nodes to transmit over the same wire pair.

How does asynchronous transmission work. Draw one frame of asynchronous serial data.

Asynchronous transmission is used in systems where one character is sent at a time, and the interval of time between each byte transmission may vary. The transmission format uses one start bit at the beginning and one or two stop bits at the end of each character (Figure 9-2). The receiver synchronizes its clock upon receiving the start bit and then samples the data bits (either seven or eight, depending on the system configuration). Upon receiving the stop bit(s) in the correct sequence, the receiver assumes that the transfer was successful and that it has a valid character. If it did not receive an appropriate stop sequence, the receiver assumes that its clock drifted out of phase, and a framing error or bit-misalignment error is declared. It's up to the application software to check for such errors and take appropriate action. The conversion from parallel to serial format is usually accomplished by dedicated UART hardware, but in systems where only parallel I/O is available, the conversion may be performed by software, which toggles a single bit of a parallel I/O port acting as the serial line.

Explain Full-Duplex RS-485 and draw a typical Full-Duplex RS-485 application circuit.

Figure 4 shows an example of an RS-485 bus connected in a full-duplex bus configuration. This configuration is also known as a 4-wire RS-485 network connected in a multipoint master/slave configuration. Full-duplex RS-485 allows for simultaneous communication in both directions between master and slave nodes.

What three modes/features does the switching reg. offer?

Boost (higher voltage out than in) Buck (lower voltage out than in) Invert

Explain how the SPI transmission works. Make a drawing!

Both masters and slaves contain a serial shift register. The master starts a transfer of a byte by writing it to its SPI shift register. As the register transmits the byte to the slave on the MOSI signal line, the slave transfers the contents of its shift register back to the master on the MISO signal line (Figure 7-2). In this way, the contents of the two shift registers are exchanged. Both a write and a read operation are performed with the slave simultaneously. SPI can therefore be a very efficient protocol. If only a write operation is desired, the master just ignores the byte it receives. Conversely, if the master just wishes to read a byte from the slave, it must transfer a dummy byte in order to initiate a slave transmission.

What is the most commonly used switching converter?

Buck regulator The most commonly used switching converter is the Buck, which is used to down-convert a DC voltage to a lower DC voltage of the same polarity. This is essential in systems that use distributed power rails (like 24V to 48V), which must be locally converted to 15V, 12V or 5V with very little power loss.

What is is called when you use the address pins in combination with the datapins and a latch to address a 16bit address, and still be able to use the 8-bit data pins?

Bus multiplexing

Explain Remote Data Request (CAN):

By sending a REMOTE FRAME a node requiring data may request another node to send the corresponding DATA FRAME. The DATA FRAME and the corresponding REMOTE FRAME are named by the same IDENTIFIER.

How long can a RS-232C support data transmission over cable?

Cable lengths of up to 25 meters a

What is line- and load-regulation?

Line-regulation: a measure of the ability of the regulator to maintain its output voltage given changes in the input line voltage. Load-regulation: a measure of the ability of the regulator to maintain its output voltage given changes in the load.

Types of regulators?

Linear reg., switching reg. and charge pumps

Which regulator gives the smalles amount of output noise?

Linear regulators

Explain Fault Confinement (CAN):

CAN nodes are able to distinguish short disturbances from permanent failures. Defective nodes are switched off.

What layers of the ISO-OSI model does CAN specifie?

CAN specifies only the physical and data-link layers of the ISO-OSI model, with higher layers left to the specific implementation.

RISC vs CISC

CISC v RISC is largely a historical debate. Modern processors are pretty much all RISC. Even CISC instruction sets (x86-64) are translated to RISC microcode on chip prior to execution. But the general differences are: CISC [Complex instruction set Computing]- larger, more feature-rich instruction set (more operations, addressing modes, etc.). slower clock speeds. fewer general purpose registers. Examples: x86 variants RISC [Reduced instruction set Computing] - smaller, simpler instruction set. faster clock speeds. more general purpose registers. Examples: MIPS, Itanium, PowerPC Practical implications: An equivalent program implemented in CISC will most likely be shorter than a program implemented in RISC (because RISC combines multiple simple instructions to replicate the complex instructions provided by CISC). RISC CPUs generally run at faster clock speeds than CISC because max clock period is dictated by the slowest step of the pipeline (more complex instructions are slower).

Name two instruction sets and compare them:

CISC: Oldest, more complex instructions, slower, less code needs to be written RISC: Newer, less complex instructions which makes it faster but requires more lines of code.

The Universal Serial Bus specification defines four transfer/endpoint types, explain briefly the purpose of each of them.

Control Transfers: Control transfers are typically used for command and status operations. They are essential to set up a USB device with all enumeration functions being performed using control transfers. They are typically bursty, random packets which are initiated by the host and use best effort delivery. The packet length of control transfers in low speed devices must be 8 bytes, high speed devices allow a packet size of 8, 16, 32 or 64 bytes and full speed devices must have a packet size of 64 bytes. Interrupt Transfers: Any one who has had experience of interrupt requests on microcontrollers will know that interrupts are device generated. However under USB if a device requires the attention of the host, it must wait until the host polls it before it can report that it needs urgent attention! Interrupt transfers are typically non-periodic, small device "initiated" communication requiring bounded latency. An Interrupt request is queued by the device until the host polls the USB device asking for data. x Isochronous Transfers: Isochronous transfers occur continuously and periodically. They typically contain time sensitive information, such as an audio or video stream. If there were a delay or retry of data in an audio stream, then you would expect some erratic audio containing glitches. The beat may no longer be in sync. However if a packet or frame was dropped every now and again, it is less likely to be noticed by the listener. Bulk Transfers: Bulk transfers can be used for large bursty data. Such examples could include a print-job sent to a printer or an image generated from a scanner. Bulk transfers provide error correction in the form of a CRC16 field on the data payload and error detection/re-transmission mechanisms ensuring data is transmitted and received without error. Bulk transfers will use spare un-allocated bandwidth on the bus after all other transactions have been allocated. If the bus is busy with isochronous and/or interrupt then bulk data may slowly trickle over the bus. As a result Bulk transfers should only be used for time insensitive communication as there is no guarantee of latency.

Explain Error Signaling and Recovery Time (CAN):

Corrupted messages are flagged by any node detecting an error. Such messages are aborted and will be retransmitted automatically. The recovery time from detecting an error until the start of the next message is at most 31 bit times, if there is no further error.

Features with ZigBee?

Low power consumption Great range Low data transfer rate Simple complexity

What is Direct Memory Access (DMA)?

DMA allows data to be transferred from I/O devices to memory directly without the continuous involvement of the processor. DMA is used in high-speed systems, where the rate of data transfer is important. Not all processors support DMA.

Explain what DRAM is

DRAM uses arrays of what are essentially capacitors to hold individual bits of data. The capacitor arrays will hold their charge only for a short period before it begins to diminish. Therefore, DRAMs need continuous refreshing, every few milliseconds or so. This perpetual need for refreshing requires additional support and can delay processor access to the memory. If a processor access conflicts with the need to refresh the array, the refresh cycle must take precedence. DRAMs are the highest-capacity memory devices available and come in a wide and diverse variety of subspecies. Interfacing DRAMs to small microcontrollers is generally not possible, and certainly not practical. Most processors with large address spaces include support for DRAMs. Connecting DRAMs to such processors is simply a case of "connecting the dots" (or pins, as the case may be). For those processors that do not include DRAM support, special DRAM controller chips are available that make interfacing the DRAMs very simple indeed.

Name four VMEbus signal lines

Data Transfer Bus Some data transfer bus lines are used for more than one purpose. Please refer to the VMEbus specification if greater detail is required. Addressing lines are driven by a bus master and monitored by a bus slave. The master drives AS* (Address Strobe) to indicate a valid address on the bus. Data lines are used to transfer information across the bus. Transfer size (8-bit, 16-bit, 32-bit) is determined by the state of the LWORD*, DS0*, and DS1* lines. Direction of the transfer is determined by the WRITE* line's state. All data transfers are terminated by asserting one of the following signals: DTACK* (a data transfer acknowledgment indicating a successful transfer), BERR* (a Bus Error indicating a bus timeout or an error), or VME64 RETRY* (retry in which the master should automatically release the bus and try the transfer again later). VME64 multiplexes the addressing and data lines. When using A64 (long addressing) modes, D31 - D00 are also used as addressing lines. When using D64 transfers, the A31 - A01 and LWORD* lines are also used as data lines. Priority Interrupt Bus The priority interrupt bus consists of interrupt request lines (IRQ7* - IRQ1*), the IACK* line, and IACK daisy-chain lines (IACKIN* and IACKOUT*). This bus is used to assert an interrupt. It is also used in conjunction with the data transfer bus to acknowledge an interrupt. Data Transfer Arbitration Bus The data transfer arbitration bus is used by a bus master to request permission from the System Controller to use the bus. The arbiter in the System Controller determines which master will be granted the bus. Utility Bus The utility bus contains all system monitoring lines, including SYSRESET*, BERR*, SYSFAIL* and ACFAIL*. SYSRESET* is used to reset the VMEbus system. BERR* is used to terminate a bus cycle. SYSFAIL* is a utility signal that can be used for system diagnostics. ACFAIL* is asserted when the AC line voltage stops.

How is data transferred on the 1-Wire net?

Data on the 1-Wire net is transferred by time slots. For example, to write a logic one to a slave, the master pulls the bus low for 15μs or less. To write a logic zero, the master pulls the bus low for at least 60μs to provide timing margin for worst-case conditions. A system clock is not required, as each 1-Wire part is self-clocked by its own internal oscillator synchronized to the falling edge of the master. Power for chip operation is derived from the bus during idle communication periods when the DATA line is at 5V by including a half-wave rectifier on each slave. Whenever the data line is pulled high, the diode in the half- wave rectifier turns on and charges an on-chip capacitor. When the voltage on the net drops below the voltage on the capacitor, the diode is reverse biased, which isolates the charge. The resulting charge provides the energy source to power the slave during the intervals when the net is pulled low. The amount of charge lost during these periods is replenished when the data line returns high. This concept of "stealing" power from the net by a half-wave rectifier is referred to as "parasite power." When communicating, the master resets the network by holding the bus low for at least 480μs, releasing it, and then looking for a responding presence pulse from a slave connected to the line. If a presence pulse is detected, it then accesses the slave by calling its address, controlling the information transfer by generating time slots and examining the response from the slave. Once this handshake is successful, the master issues necessary device-specific commands and performs any needed data transfers between it and the slave. The master can select a single slave from many on the net because of its unique digital address.

What are the common USB packets fields?

Data on the USBus is transmitted LSBit first. USB packets consist of the following fields, Sync All packets must start with a sync field. The sync field is 8 bits long, which is used to synchronise the clock of the receiver with the transmitter. The last two bits indicate where the PID fields starts. PID PID stands for Packet ID. This field is used to identify the type of packet that is being sent. The following table shows the possible values. There is 4 bits to the PID, however to insure it is received correctly, the 4 bits are complemented and repeated, making an 8 bit PID in total. The resulting format is shown below. ADDR The address field specifies which device the packet is designated for. Being 7 bits in length allows for 127 devices to be supported. Address 0 is not valid, as any device which is not yet assigned an address must respond to packets sent to address zero. ENDP The endpoint field is made up of 4 bits, allowing 16 possible endpoints. Low speed devices, however can only have 2 endpoint additional addresses on top of the default pipe. (4 Endpoints Max) CRC Cyclic Redundancy Checks are performed on the data within the packet payload. All token packets have a 5 bit CRC while data packets have a 16 bit CRC. EOP End of packet. Signalled by a Single Ended Zero (SE0) for approximately 2 bit times followed by a J for 1 bit time.

IC designer benefits I2C

Designers of microcontrollers are frequently under pressure to conserve output pins. The I2C protocol allows connection of a wide variety of peripherals without the need for separate addressing or chip enable signals. Additionally, a microcontroller that includes an I2C interface is more successful in the marketplace due to the wide variety of existing peripheral devices available.

Difference between DSSS and FHSS?

Direct Sequence Spread Spectrum: -PRN (Pseudo Random Noise) modulates directly XOR - Phase shift modulation of base signal Frequency Hopping Spread Spectrum - PRN (Pseudo Random Noise) code basis for random hopping through a set of valid transmitter frequencies - Frequency modulation of baseband signal (FSK)

Explain what EEROM is

EEROM is Electrically Erasable Read-Only Memory, also known as EEPROM (Electrically Erasable Programmable Read-Only Memory). Very rarely, it is also called Electrically Alterable Read-Only Memory (EAROM). EEROM can be pronounced as either "e-e ROM" or "e-squared ROM," or sometimes just "e- squared" for short. EEROMs can be erased and reprogrammed in-circuit. Their capacity is significantly smaller than standard ROM (typically only a few kilobytes), and so they are not suited to holding firmware. Instead, they are typically used for holding system parameters and mode information to be retained during power-off. It is common for many microcontrollers to incorporate a small EEROM on-chip for holding system parameters. This is especially useful in embedded systems and may be used for storing network addresses, configuration settings, serial numbers, servicing records, and so on.

Why does the CAN need a termination resistor? Draw a simple CAN bus

Each end of the bus requires termination resistors to prevent transmission reflections (Figure 12-2).

What is a Multi-Master RS-485 Systems

Each node in a multi-master type RS-485 system can initiate its own transmission creating the potential for data collisions. This type system requires the designer to implement a more sophisticated method of error detection, including methods such as line contention detection, acknowledgement of transmissions and a system for resending corrupted data.

Unbalanced Line Drivers (RS-232). Make drawing

Each signal that transmits in an RS-232 unbalanced data transmission system appears on the interface connector as a voltage with reference to a signal ground. For example, the transmitted data (TD) from a DTE device appears on pin 2 with respect to pin 7 (signal ground) on a DB-25 connector. This voltage will be negative if the line is idle and alternate between that negative level and a positive level when data is sent with a magnitude of ±5 to ±15 volts. The RS- 232 receiver typically operates within the voltage range of +3 to +12 and -3 to -12 volts as shown in Figure 1.1.

(USB) What is an endpoint?

Endpoints can be described as sources or sinks of data. As the bus is host centric, endpoints occur at the end of the communications channel at the USB function. At the software layer, your device driver may send a packet to your devices EP1 for example. As the data is flowing out from the host, it will end up in the EP1 OUT buffer. Your firmware will then at its leisure read this data. If it wants to return data, the function cannot simply write to the bus as the bus is controlled by the host. Therefore it writes data to EP1 IN which sits in the buffer until such time when the host sends a IN packet to that endpoint requesting the data. Endpoints can also be seen as the interface between the hardware of the function device and the firmware running on the function device. All devices must support endpoint zero. This is the endpoint which receives all of the devices control and status requests during enumeration and throughout the duration while the device is operational on the bus.

What is enumeration? (USB)

Enumeration is the process of determining what device has just been connected to the bus and what parameters it requires such as power consumption, number and type of endpoint(s), class of product etc. The host will then assign the device an address and enable a configuration allowing the device to transfer data on the bus. A fairly generic enumeration process is detailed in section 9.1.2 of the USB specification. However when writing USB firmware for the first time, it is handy to know exactly how the host responds during enumeration, rather than the general enumeration process detailed in the specification. A common Windows enumeration involves the following steps, 1. The host or hub detects the connection of a new device via the device's pull up resistors on the data pair. The host waits for at least 100ms allowing for the plug to be inserted fully and for power to stabilise on the device. 2. Host issues a reset placing the device is the default state. The device may now respond to the default address zero. 3. The MS Windows host asks for the first 64 bytes of the Device 4. After receiving the first 8 bytes of the Device Descriptor, it immediately issues another bus reset. 5. The host now issues a Set Address command, placing the device in the addressed state. 6. The host asks for the entire 18 bytes of the Device Descriptor. 7. It then asks for 9 bytes of the Configuration Descriptor to determine the overall size. 8. The host asks for 255 bytes of the Configuration Descriptor. 9. Host asks for any String Descriptors if they were specified. At the end descriptors again before it issues a Set Configuration request. of Step 9, Windows will ask for a driver for your device. It is then common to see it request all the The above enumeration process is common to Windows 2000, Windows XP and Windows 98 SE. Step 4 often confuses people writing firmware for the first time. The Host asks for the first 64 bytes of the device descriptor, so when the host resets your device after it receives the first 8 bytes, it is only natural to think there is something wrong with your device descriptor or how your firmware handles the request. However as many will tell you, if you keep persisting by implementing the Set Address Command it will pay off by asking for a full 18 bytes of device descriptor next. Normally when something is wrong with a descriptor or how it is being sent, the host will attempt to read it three times with long pauses in between requests. After the third attempt, the host gives up reporting an error with your device.

What is a setup packet? (USB)

Every USB device must respond to setup packets on the default pipe. The setup packets are used for detection and configuration of the device and carry out common functions such as setting the USB device's address, requesting a device descriptor or checking the status of a endpoint.

How does the UART work? Draw a functional diagram of a UART.

Figure 9-1 shows a functional diagram of a UART. It consists of two sections: a receiver (Rx) that converts a serial bit stream to parallel data for the microprocessor and a transmitter (Tx) that converts parallel data from a microprocessor into serial form for transmission. The UART also provides status information, such as whether the receiver is full (data has arrived) or that the transmitter is empty (a pending transmission has completed). Many microcontrollers incorporate UARTs on-chip, but for larger systems, the UART is often a separate device. Serial devices send data one bit at a time, so normal "parallel" data must first be converted to serial form before transfer. Serial transmission consists of breaking down bytes of data into single bits and shifting them out of the device one at a time. A UART's transmitter is essentially just a parallel-to-serial converter with extra features. The essence of the UART transmitter is a shift register that is loaded in parallel, and then each bit is sequentially shifted out of the device on each pulse of the serial clock. Conversely, the receiver accepts a serial bit stream into a shift register, and then this is read out in parallel by the processor.

Explain shortly an Flash analog-to-digital converter.

Flash analog-to-digital converters, also known as parallel ADCs, are the fastest way to convert an analog signal to a digital signal. Flash ADCs are suitable for applications requiring very large bandwidths. However, these converters consume considerable power, have relatively low resolution, and can be quite expensive. This limits them to high-frequency applications that typically cannot be addressed any other way. Typical examples include data acquisition, satellite communication, radar processing, sampling oscilloscopes, and high-density disk drives. Flash ADCs are made by cascading high-speed comparators. Figure 1 shows a typical flash ADC block diagram. For an N-bit converter, the circuit employs 2N-1 comparators. A resistive-divider with 2N resistors provides the reference voltage. The reference voltage for each comparator is one least significant bit (LSB) greater than the reference voltage for the comparator immediately below it. Each comparator produces a 1 when its analog input voltage is higher than the reference voltage applied to it. Otherwise, the comparator output is 0. Thus, if the analog input is between VX4 and VX5, comparators X1 through X4 produce 1s and the remaining comparators produce 0s. The point where the code changes from ones to zeros is the point at which the input signal becomes smaller than the respective comparator reference-voltage levels.

Explain what FLASH is

Flash is the newest ROM technology and is now dominant. Flash memory has the reprogrammability of EEROM and the large capacity of standard ROMs. Flash chips are sometimes referred to as "flash ROMs" or "flash RAMs." Since they are not like standard ROMs or standard RAMs, I prefer just to call them "flash" and save on the confusion. Flash is normally organized as sectors and has the advantage that individual sectors may be erased and rewritten without affecting the contents of the rest of the device. Typically, before a sector can be written, it must be erased. It can't just be written over as with a RAM. There are several different flash technologies, and the erasing and programming requirements of flash devices vary from manufacturer to manufacturer.

SPI has four modes of operation, depending on clock polarity and clock phase. Explain

For low clock polarity, the clock (SCK) is low when idle and toggles high during a transfer. When configured for high clock polarity, the clock is high when idle and toggles low during a transfer. The two clock phases are known as clock phase zero and clock phase one. For clock phase zero, MOSI and MISO outputs are valid on the rising edge of the clock (SCK) if the clock polarity is low (Figure 7-4). If the clock polarity is high, these outputs are valid on the falling edge of SCK, for clock phase zero (Figure 7-5). The "X" bit output on MISO is an undefined extra bit and is a consequence of the SPI interface. You don't need to worry about it, as the SPI interfaces ignore it. Conversely, for clock phase one, the opposite is true. MOSI and MISO are valid on the falling edge of the clock if clock polarity is low (Figure 7-6). They are valid on the rising edge of the clock if the clock polarity is high (Figure 7-7).

Explain Half-Duplex RS-485 and draw a typical Half-Duplex RS-485 application circuit.

Half-duplex RS-485 links have multiple drivers and receivers on the same signal path. This is the reason why RS-485 transceivers must have driver/receiver enable pins enabling only one driver to send data at a time. See Figure 3 for a half-duplex bus configuration. This configuration is also known as a 2-wire RS-485 network connected in a multipoint configuration and allows for data transmission in both directions, but only in one direction at a time.

Hardware handshaking in RS-232C

Hardware handshaking in RS-232C uses two signals, RTS (Request To Send) and CTS (Clear To Send). When the transmitter wishes to send, it asserts RTS, indicating to the receiver that there is pending data. The receiver asserts CTS when it is ready, indicating to the transmitter that it may send. In this way, the flow of data is limited to the rate at which it may be processed.

Harvard architecture vs Von Neumann architecture

Harvard architecture has separate data and instruction busses, allowing transfers to be performed simultaneously on both busses. A von Neumann architecture has only one bus which is used for both data transfers and instruction fetches, and therefore data transfers and instruction fetches must be scheduled - they can not be performed at the same time. It is possible to have two separate memory systems for a Harvard architecture. As long as data and instructions can be fed in at the same time, then it doesn't matter whether it comes from a cache or memory. But there are problems with this. Compilers generally embed data (literal pools) within the code, and it is often also necessary to be able to write to the instruction memory space, for example in the case of self modifying code, or, if an ARM debugger is used, to set software breakpoints in memory. If there are two completely separate, isolated memory systems, this is not possible. There must be some kind of bridge between the memory systems to allow this. Using a simple, unified memory system together with a Harvard architecture is highly inefficient. Unless it is possible to feed data into both busses at the same time, it might be better to use a von Neumann architecture processor.

What are the speeds of High speed, full speed and low speed? (USB)

High Speed - 480Mbits/s Full Speed - 12Mbits/s Low Speed - 1.5Mbits/s

What is I2C, and how does it work? Draw a basic I2C network.

I2C (Inter-Integrated Circuit) bus is a very cheap yet effective network used to interconnect peripheral devices within small-scale embedded systems. It is sometimes also known as IIC and has been in existence for more than 20 years. It is the equivalent of SPI, but its operation is somewhat different. I2C uses two wires to connect multiple devices in a multi-drop bus. The bus is bidirectional, low-speed, and synchronous to a common clock. Devices may be attached or detached from the I2C bus without affecting other devices. Several manufacturers, such as Microchip, Philips, Intel, and others produce small microcontrollers with I2C built in. The data rate of I2C is somewhat slower than SPI, at 100 kbps in standard mode, and 400 kbps in fast mode. The two wires used to interconnect with I2C are SDA (serial data) and SCL (serial clock). Both lines are open-drain.[*] They are connected to a positive supply via a pull-up resistor and therefore remain high when not in use. A device using the I2C bus to communicate drives the lines low or leaves them pulled high as appropriate. Each device connected to the I2C bus has a unique address and can operate as either a transmitter (a bus master), a receiver (a bus slave), or both (Figure 8-1). I2C is a multi-master bus, meaning that more than one device may assume the role of bus master. [*] An open-drain or open-collector pin has output drivers that can only pull the signal line to ground. They cannot drive it high. This has the advantage that more than one device connected to a signal line may pull it low. If this were not the case, one device attempting to pull the line low while another tried to pull it high would result in a short circuit, with disastrous results. Interrupt lines are typically open-collector. All open-collector signals need a pull-up resistor and are active low. The idle state (when no device is asserting) is to be pulled high by the resistor.

Designer benefits of I2C

I2C-bus compatible ICs allow a system design to progress rapidly directly from a functional block diagram to a prototype. Moreover, since they 'clip' directly onto the I2C-bus without any additional external interfacing, they allow a prototype system to be modified or upgraded simply by 'clipping' or 'unclipping' ICs to or from the bus. Here are some of the features of I2C-bus compatible ICs that are particularly attractive to designers: Functional blocks on the block diagram correspond with the actual ICs; designs proceed rapidly from block diagram to final schematic. No need to design bus interfaces because the I2C-bus interface is already integrated on-chip. Integrated addressing and data-transfer protocol allow systems to be completely software-defined. The same IC types can often be used in many different applications. Design-time reduces as designers quickly become familiar with the frequently used functional blocks represented by I2C-bus compatible ICs. ICs can be added to or removed from a system without affecting any other circuits on the bus. Fault diagnosis and debugging are simple; malfunctions can be immediately traced. Software development time can be reduced by assembling a library of reusable software modules. In addition to these advantages, the CMOS ICs in the I2C-bus compatible range offer designers special features which are particularly attractive for portable equipment and battery-backed systems. They all have: • Extremely low current consumption • High noise immunity • Wide supply voltage range • Wide operating temperature range.

Manufacturer benefits I2C:

I2C-bus compatible ICs not only assist designers, they also give a wide range of benefits to equipment manufacturers because: The simple 2-wire serial I2C-bus minimizes interconnections so ICs have fewer pins and there are not so many PCB tracks; result — smaller and less expensive PCBs. The completely integrated I2C-bus protocol eliminates the need for address decoders and other 'glue logic'. The multi-master capability of the I2C-bus allows rapid testing and alignment of end-user equipment via external connections to an assembly line. The availability of I2C-bus compatible ICs in various leadless packages reduces space requirements even more.

What is arbitration (I2C):

If two or more masters try to put information onto the bus, the first to produce a 'one' when the other produces a 'zero' loses the arbitration. The clock signals during arbitration are a synchronized combination of the clocks generated by the masters using the wired-AND connection to the SCL line

Draw and explain how a H-bridge works

If we send A high, the transistor Q4 turns on and connects the right "side" of the motor to ground. If we then send PWM-A high, the transistor Q1 turns on. Thus, the left "side" of the motor is connected to V+, and the motor spins. By generating a PWM signal on PWM-A, we can control the speed of the motor in that direction. Conversely, by leaving A and PWM-A low and setting B and PWM-B high, transistors Q2 and Q3 turn on, and the motor spins in the reverse direction. By generating a PWM signal on PWM-B, we can control the speed in the reverse direction.

Balanced Line Drivers (RS-422/RS-485). Make drawing

In a balanced differential system the voltage produced by the driver appears across a pair of signal lines that transmit only one signal. Figure 1.2 shows a schematic symbol for a balanced line driver and the voltages that exist. A balanced line driver will produce a voltage from 2 to 6 volts across its A and B output terminals and will have a signal ground (C) connection. Although proper connection to the signal ground is important, it isn't used by a balanced line receiver in determining the logic state of the data line. A balanced line driver can also have an input signal called an "Enable" signal. The purpose of this signal is to connect the driver to its output terminals, A and B. If the "Enable" signal is OFF, one can consider the driver as disconnected from the transmission line. An RS-485 driver must have the "Enable" control signal. An RS-422 driver may have this signal, but it is not always required. The disconnected or "disabled" condition of the line driver usually is referred to as the "tristate1" condition of the driver.

Buck regulator CONTINUOUS vs. DISCONTINUOUS OPERATION

In most Buck regulator applications, the inductor current never drops to zero during full-load operation (this is defined as continuous mode operation). Overall performance is usually better using continuous mode, and it allows maximum output power to be obtained from a given input voltage and switch current rating. In applications where the maximum load current is fairly low, it can be advantageous to design for discontinuous mode operation. In these cases, operating in discontinuous mode can result in a smaller overall converter size (because a smaller inductor can be used). Discontinuous mode operation at lower load current values is generally harmless, and even converters designed for continuous mode operation at full load will become discontinuous as the load current is decreased (usually causing no problems).

When choosing a regulator, what requirements must be evaluated?

Maximum Load Current Type of Input Voltage Source (Battery or AC) Output Voltage Precision (Tolerance) Quiescent (Idling) Current Special Features (Shutdown Pin, Error Flag, etc.)

Explain Safety (CAN):

In order to achieve the utmost safety of data transfer, powerful measures for error detection, signalling and self-checking are implemented in every CAN node. Error Detection For detecting errors the following measures have been taken: - Monitoring (transmitters compare the bit levels to be transmitted with the bit levels detected on the bus) - Cyclic Redundancy Check - Bit Stuffing - Message Frame Check Performance of Error Detection The error detection mechanisms have the following properties: - all global errors are detected. - all local errors at transmitters are detected. - up to 5 randomly distributed errors in a message are detected. - burst errors of length less than 15 in a message are detected. - errors of any odd number in a message are detected.

Draw and explain a sample packet, transferring one byte of data. I2C

Instead, each device on the bus has a unique address, and the packet transmission begins with address bits, followed by the data. An address byte consists of seven address bits, followed by a direction bit. If the direction bit is a 0, the transmission is a write cycle and the selected slave will accept the data as input. If the direction bit is a 1, then the request is for the slave to transfer data back to the master. A sample packet, transferring one byte of data, is shown in Figure 8-6.

What is an Interrupt?

Interrupts (also known as traps or exceptions in some processors) are a technique of diverting the processor from the execution of the current program so that it may deal with some event that has occurred. Such an event may be an error from a peripheral, or simply that an I/O device has finished the last task it was given and is now ready for another. An interrupt is generated in your computer every time you type a key or move the mouse. You can think of it as a hardware-generated function call. When an interrupt occurs, the usual procedure is for the processor to save its state by pushing its registers and program counter onto the stack. The processor then loads an interrupt vector into the program counter. The interrupt vector is the address at which an interrupt service routine (ISR) lies. Thus, loading the vector into the program counter causes the processor to begin execution of the ISR, performing whatever service the interrupting device required. The last instruction of an ISR is always a Return from Interrupt instruction. This causes the processor to reload its saved state (registers and program counter) from the stack and resume its original program. Interrupts are largely transparent to the original program. This means that the original program is completely "unaware" that the processor was interrupted, save for a lost interval of time.

What is IrDA?

IrDA is the infrared transmission standard commonly used in computers and peripherals. IrDA, which stands for "Infrared Data Association," is a consortium of over 150 companies that maintain and develop the standard. With all that in mind, IrDA is a point-to-point protocol that uses asynchronous serial transmission over short distances. The initial IrDA specification (1.0) supported data rates of between 2,400 bps and 115.2 kbps over distances of one meter, although some IrDA transceivers can achieve greater distances than this. Initial IR communication takes place at 9,600 bps, and devices negotiate the data rate up or down, depending on their capabilities and needs. Unlike RS-232C, the user does not need to set, know about, or even care what bit rate is being used in communication.

Does the RS-485 and RS-422 cable need shielding?

It is often hard to quantify if shielded cable is required in an application or not. Since the added cost of shielded cable is usually minimal it is worth installing the first time.

Features with Bluetooth?

Medium power consumtion Low range Medium data transfer rate Medium complexity

What are the different RS-485 and RS-422 terminations. What are the benefits of each type?

No Termination The time required for a signal to propagate down the line to a receiver determines if a line is considered a transmission line. Physically long wires have longer propagation times, whereas physically short wires have shorter propagation times. When the propagation time is short relative to the data bit duration, the effect on the signal quality is minimized. A cable is not seen as a transmission line if the signal rise time is more than four times the propagation delay of the cable. Parallel Termination When two or more drivers share a pair of wires, each end of the link has a termination resistor equal to the characteristic impedance of the cable. There should be no more than two terminating resistors in the network regardless of how many nodes are connected. In a half-duplex configuration, both ends of the cable must be terminated (see Figure 3). In a full duplex configuration only the master receiver and most remote slave receiver need to be terminated. AC Termination AC termination is used to reduce the power consumption of idle links as well as to reduce ringing voltages. The negative effect though is a reduction in cable length and bit rate. A resistor and capacitor can be placed in series across the bus (between A and B) as shown in Figure 5. The Capacitor CT is selected by using the following formula:

What are the limitations of parity checks? Give an example.

Now, what if the medium was particularly noisy and two bits were corrupted? Again, if we sent %01000000 with even parity (computed parity bit = 1), and this was corrupted along the way to be %01001001, the receiver would calculate the even parity of the byte to be 1. The transmission was corrupted, but no parity error would be detected! As you can see, the usefulness of this form of error detection is extremely limited, and, for this reason, more complicated error detection (and correction) schemes are often implemented.

Name the features of the I2C-bus:

Only two bus lines are required; a serial data line (SDA) and a serial clock line (SCL). Each device connected to the bus is software addressable by a unique address and simple master/slave relationships exist at all times; masters can operate as master-transmitters or as master-receivers. It is a true multi master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer. Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 kbit/s in the Standard-mode, up to 400 kbit/s in the Fast-mode, up to 1 Mbit/s in Fast-mode Plus, or up to 3.4 Mbit/s in the High-speed mode. Serial, 8-bit oriented, unidirectional data transfers up to 5 Mbit/s in Ultra Fast-mode On-chip filtering rejects spikes on the bus data line to preserve data integrity. The number of ICs that can be connected to the same bus is limited only by a maximum bus capacitance. More capacitance may be allowed under some conditions.

What is PC/104 and what is it's benefits?

PC/104 is an embedded computer standard defined by its compact footprint and its stacking bus structure. In essence, PC/104 is a modular, ruggedized version of the PC. Instead of using a backplane, PC/104 modules mate together via stackable ISA, PCI, and PCIe bus connectors. The stackable connectors and asymmetric corner mounting holes create a compact and modular rugged system. PC/104 leverages large PC hardware and software markets by following mainstream PC bus development. This reduces time-to-market, and minimizes development costs. Completely defined bus pinouts enable interchangeability and interoperability. This means that users and system designers can choose from a wide array of specialized PC/104 modules to tailor a system to fit their project requirements. Stackable: The design and location of the PC/104 connectors (ISA, PCI, and PCIe) allow PC/104 modules to be connected or stacked like building blocks. A PC/104 stack might include a CPU (single board computer), a power supply module, and peripheral modules such as data collection modules, network modules, or storage devices. Modules within a PC/104 stack are joined by stand-offs. Rugged: PC/104 is inherently rugged. A small footprint and corner mounting holes ensure minimum PCB (printed circuit board) flex in high-vibration scenarios. Many modules are manufactured with extended temperature components, allowing operation from -40 to +85°C. Learn more about RTD's quality and process control. Compact: PC/104 modules occupy a small footprint, but offer highly powerful computer processing and data-collection capabilities. Some applications might require one PC/104 single board computer (SBC) and a power supply. Advanced applications can employ an SBC and multiple special-purpose peripheral modules such as GPS receivers, Ethernet switches, video controllers and data collection cards. Interoperable: PC/104 modules are designed to work together. Users can tailor a system for their specific requirements using multiple PC/104 modules from different PC/104 manufacturers. The differences between PC/104 and the "normal" PC are primarily mechanical; there are no software differences. The PC/104 specification (available from the PC/104 Consortium) defines a compact form factor, a self-stacking 104-signal pin-and-socket connector bus (to eliminate backplanes and card cages), and reduced bus drive (for lower power consumption and minimized components).

What are the two common "types" of linear regulators? How do they differ?

Standard and Low DropOut (LDO). LDO requires a smaller difference between line and load voltage, and is typically used when powered by batteries

Explain what RAM is

RAM stands for Random Access Memory. This is a bit of a misnomer, since most (all) computer memory may be considered "random access." RAM is the "working memory" in the computer system. It is where the processor may easily write data for temporary storage. RAM is generally volatile, losing its contents when the system loses power. Any information stored in RAM that must be retained must be written to some form of permanent storage before the system powers down. There are special nonvolatile RAMs that integrate a battery-backup system, such that the RAM remains powered even when the rest of the computer system has shut down. RAMs generally fall into two categories: static RAM (also known as SRAM) and dynamic RAM (also known as DRAM).

Explain what ROM is

ROM stands for Read-Only Memory. This is also a bit of a misnomer, since many (modern) ROMs can also be written to. ROMs are nonvolatile memory, requiring no power to retain their contents. They are generally slower than RAM, and considerably slower than fast static RAM. The primary purpose of ROM within a system is to hold the code (and sometimes data) that needs to be present at power-up. Such software is generally known as firmware and contains software to initialize the computer by placing I/O devices into a known state. It may contain either a bootloader program to load an operating system off disk or network or, in the case of an embedded system, it may contain the application itself. One-Time Programmable (OTP) ROMs, as the name implies, can be burned once only. Computer manufacturers typically use them in systems where the firmware is stable and the product is shipping in bulk to customers. Mask-programmable ROMs are also one-time programmable, but unlike OTPs, they are burned by the chip manufacturer prior to shipping. Like OTPs, they are used once the software is known to be stable and have the advantage of lowering production costs for large shipments.

Difference between RS-232, RS-422 and RS-485?

RS-232: Com. between two nodes with common ground. Full duplex. RS-422: Com. between two nodes with differential signaling. Full-duplex. RS-485: Com. between two or more nodes (one slave) and differential signaling. May be either half- or full-duplex

RS-232C is unbalanced. What does this mean?

RS-232C is unbalanced, meaning that the voltage level of a data bit being transmitted is referenced to local ground.

How long can a RS-422 support data transmission over cable?

RS-422 can support data transmission over cable lengths of up to 1,200 meters

RS-485 OR RS-422?

RS-422 is specified as a simplex multidrop standard, which means that only one driver and up to ten receivers can be connected to the same bus. If more than one driver needs to be connected on the same bus, then RS-485 is recommended. RS-485 is specified as a multipoint standard, which means up to 32 transceivers can be connected on the same bus.

What is a register

Registers are the internal (working) storage for the processor. The number of registers varies significantly among processor architectures. Typically, the processor will have one or more accumulators. These are registers that may have arithmetic operations performed on them. In some architectures, all the registers function as accumulators, whereas in others, some registers are dedicated for storage only and have limited functionality. Some processors have index registers that can function as pointers into the memory space. In some architectures, all general-purpose registers can act as index registers; in others, dedicated index registers exist. All processors have a program counter (also known as an instruction pointer) that tracks the location in memory of the next instruction to be fetched and executed. All processors have a status register (also known as a condition-code register, or CCR) that consists of various status bits (flags) that reflect the current operational state. Such flags might indicate whether the result of the last operation was zero or negative, whether a carry occurred, if an interrupt is being serviced, etc.

Does I2C have a chip select?

SPI uses a separate chip select to enable a receiving slave. Each SPI slave has a separate chip select that is generated by the master. I2C does not have such a selection mechanism. Instead, each device on the bus has a unique address, and the packet transmission begins with address bits, followed by the data.

Explain what SRAM is

SRAMs use pairs of logic gates to hold each bit of data. SRAMs are the fastest form of RAM available, require little external support circuitry, and have relatively low power consumption. Their drawbacks are that their capacity is considerably less than DRAM, while being much more expensive. Their relatively low capacity requires more chips to be used to implement the same amount of memory. A modern PC built using nothing but SRAM would be a considerably bigger machine and would cost a small fortune to produce. (It would be very fast, however.)

Name some special features LDO can have.

Shutdown: A low-power shutdown pin allows a regulator to be switched off by a logic gate or microcontroller. This feature also allows wiring a regulator for "Snap-ON/Snap-OFF" operation, which will be covered in one of the design examples presented later. Load-dump Protection: Regulators used in automotive applications need built-in protection against overvoltage transients (load-dump). In these cases the regulator usually shuts down its output during the overvoltage transient, then recovers after it has passed. Reverse Input Voltage Protection: This prevents damage to the regulator when the input voltage is reversed, essential in applications where the user can accidentally reverse the polarity of the batteries. Error Flag: This flag is used to alert monitoring or control circuitry that the output has dropped about 5% below its nominal value. It is intended as a "warning flag" that can alert a controller that supply voltage may be low enough to cause erratic operation of the CPU or associated logic circuits.

What are SIMD computers

Single-Instruction Multiple-Data (SIMD) computers are highly parallel machines, employing large arrays of simple processing elements. In an SIMD machine, each processing element has a small amount of local memory. The instructions executed by the SIMD computer are broadcast from a central instruction server to every processing element within the machine. In this way, each processor executes the same instruction as all other processing elements within the machine. Since each processor executes the instruction on its local data, all elements within the data structure are worked upon simultaneously.

There are three basic types of linear regulators covered in byggern. Name them

Standard (NPN Darlington) Regulator Low Dropout or LDO Regulator Quasi LDO Regulator

Which regulator type handles high loads better?

Switching regulators (can deliver more current)

What do we mean when we talk about termination in regards of RS-485 and RS-422? When do we need it? Draw them.

Termination is used to match impedance of a node to the impedance of the transmission line being used. When impedance are mismatched, the transmitted signal is not completely absorbed by the load and a portion is reflected back into the transmission line. If the source, transmission line and load impedance are equal these reflections are eliminated. There are disadvantages of termination as well. Termination increases load on the drivers, increases installation complexity, changes biasing requirements and makes system modification more difficult. The decision whether or not to use termination should be based on the cable length and data rate used by the system. A good rule of thumb is if the propagation delay of the data line is much less than one bit width, termination is not needed. This rule makes the assumption that reflections will damp out in several trips up and down the data line. Since the receiving UART will sample the data in the middle of the bit, it is important that the signal level be solid at that point. For example, in a system with 2000 feet of data line the propagation delay can be calculated by multiplying the cable length by the propagation velocity of the cable. This value, typically 66 to 75% of the speed of light (c), is specified by the cable manufacture.

What is the 1-Wire net?

The 1-Wire net is a low-cost bus based on a PC or micro controller communicating digitally over twisted-pair cable with 1-Wire components. The network is defined with an open-drain (wired-AND) master/slave multidrop architecture that uses a resistor pull-up to a nominal 5V supply at the master. A 1-Wire net-based system consists of three main elements: 1) a bus master with controlling software such as the TMEXTM iButton® viewer: 2) wiring and associated connectors; 3) 1-Wire devices. The system permits tight control because no node is authorized to speak unless requested by the master, and no communication is allowed between slaves except through the master.

Explain 3-stage pipeline

The ARM7TDMI-S uses a pipeline to increase the speed of the flow of instructions to the processor. This allows several operations to take place simultaneously, and the processing, and memory systems to operate continuously. A three-stage pipeline is used, so instructions are executed in three stages: Fetch Decode Execute

What does ALU stand for and what is it?

The Arithmetic Logic Unit (ALU) performs the internal arithmetic manipulation of data in the processor. The instructions that are read and executed by the processor control the data flow between the registers and the ALU. The instructions also control the arithmetic operations performed by the ALU via the ALU's control inputs.

Explain Oscillator Tolerance (CAN):

The Bit Timing requirements allow ceramic resonators to be used in applications with transmission rates of up to 125kbit/s as a rule of thumb. For the full bus speed range of the CAN protocol, a quartz oscillator is required.

Explain the boost regulator shortly

The Boost regulator takes a DC input voltage and produces a DC output voltage that is higher in value than the input (but of the same polarity).

Explain the boost regulator in detail with drawings

The Boost regulator takes a DC input voltage and produces a DC output voltage that is higher in value than the input (but of the same polarity). The Boost regulator is shown in Figure 31, along with details showing the path of current flow during the switch on and off time. Whenever the switch is on, the input voltage is forced across the inductor which causes the current through it to increase (ramp up). When the switch is off, the decreasing inductor current forces the "switch" end of the inductor to swing positive. This forward biases the diode, allowing the capacitor to charge up to a voltage that is higher than the input voltage. During steady-state operation, the inductor current flows into both the output capacitor and the load during the switch off time. When the switch is on, the load current is supplied only by the capacitor.

Explain how a buck regulator works in detail with drawings

The Buck converter uses a transistor as a switch that alternately connects and disconnects the input voltage to an inductor (see Figure 29). The lower diagrams show the current flow paths (shown as the heavy lines) when the switch is on and off. When the switch turns on, the input voltage is connected to the inductor. The difference between the input and output voltages is then forced across the inductor, causing current through the inductor to increase. During the on time, the inductor current flows into both the load and the output capacitor (the capacitor charges during this time). When the switch is turned off, the input voltage applied to the inductor is removed. However, since the current in an inductor can not change instantly, the voltage across the inductor will adjust to hold the current constant. The input end of the inductor is forced negative in voltage by the decreasing current, eventually reaching the point where the diode is turned on. The inductor current then flows through the load and back through the diode. The capacitor discharges into the load during the off time, contributing to the total current being supplied to the load (the total load current during the switch off time is the sum of the inductor and capacitor current). The shape of the current flowing in the inductor is similar to Figure 30. As explained, the current through the inductor ramps up when the switch is on, and ramps down when the switch is off. The DC load current from the regulated output is the average value of the inductor current. The peak-to-peak difference in the inductor current waveform is referred to as the inductor ripple current, and the inductor is typically selected large enough to keep this ripple current less than 20% to 30% of the rated DC current.

Explain the buck-boost (inverting) regulator shortly

The Buck-Boost or Inverting regulator takes a DC input voltage and produces a DC output voltage that is opposite in polarity to the input. The negative output voltage can be either larger or smaller in magnitude than the input voltage.

Explain the buck-boost (inverting) regulator in detail with drawings

The Buck-Boost or Inverting regulator takes a DC input voltage and produces a DC output voltage that is opposite in polarity to the input. The negative output voltage can be either larger or smaller in magnitude than the input voltage. When the switch is on, the input voltage is forced across the inductor, causing an increasing current flow through it. During the on time, the discharge of the output capacitor is the only source of load current. This requires that the charge lost from the output capacitor during the on time be replenished during the off time. When the switch turns off, the decreasing current flow in the inductor causes the voltage at the diode end to swing negative. This action turns on the diode, allowing the current in the inductor to supply both the output capacitor and the load. As shown, the load current is supplied by inductor when the switch is off, and by the output capacitor when the switch is on.

Explain Connections (CAN):

The CAN serial communication link is a bus to which a number of units may be connected. This number has no theoretical limit. Practically the total number of units will be limited by delay times and/or electrical loads on the bus line.

Explain the flyback regulator shortly

The Flyback is the most versatile of all the topologies, allowing the designer to create one or more output voltages, some of which may be opposite in polarity. Flyback converters have gained popularity in battery-powered systems, where a single voltage must be converted into the required system voltages (for example, +5V, +12V and -12V) with very high power conversion efficiency.

Explain the flyback regulator regulator in detail with drawings

The Flyback is the most versatile of all the topologies, allowing the designer to create one or more output voltages, some of which may be opposite in polarity. Flyback converters have gained popularity in battery-powered systems, where a single voltage must be converted into the required system voltages (for example, +5V, +12V and -12V) with very high power conversion efficiency. The basic single-output flyback converter is shown in Figure 33. The most important feature of the Flyback regulator is the transformer phasing, as shown by the dots on the primary and secondary windings. When the switch is on, the input voltage is forced across the transformer primary which causes an increasing flow of current through it. Note that the polarity of the voltage on the primary is dot-negative (more negative at the dotted end), causing a voltage with the same polarity to appear at the transformer secondary (the magnitude of the secondary voltage is set by the transformer seconday-to-primary turns ratio). The dot-negative voltage appearing across the secondary winding turns off the diode, preventing current flow in the secondary winding during the switch on time. During this time, the load current must be supplied by the output capacitor alone. When the switch turns off, the decreasing current flow in the primary causes the voltage at the dot end to swing positive. At the same time, the primary voltage is reflected to the secondary with the same polarity. The dot-positive voltage occurring across the secondary winding turns on the diode, allowing current to flow into both the load and the output capacitor. The output capacitor charge lost to the load during the switch on time is replenished during the switch off time. Flyback converters operate in either continuous mode (where the secondary current is always >0) or discontinuous mode (where the secondary current falls to zero on each cycle).

Draw the LOW-DROPOUT (LDO) REGULATOR. What is the dropout voltage, ground pin current and the load current?

The LDO regulator has the lowest (best) dropout voltage specification. The ground pin current of an LDO is the highest

What does the Memory Management Unit do?

The MMU offers a way of managing the translatin between the virtual memory addreses and the physical addresses.

Layered Architecture of CAN according to the OSI Reference Model with drawing

The Physical Layer defines how signals are actually transmitted and therefore deals with the description of Bit Timing, Bit Encoding, and Synchronization. Within this specification the Driver/Receiver Characteristics of the Physical Layer are not defined so as to allow transmission medium and signal level implementations to be optimized for their application. The MAC sublayer represents the kernel of the CAN protocol. It presents messages received from the LLC sublayer and accepts messages to be transmitted to the LLC sublayer. The MAC sublayer is responsible for Message Framing, Arbitration, Acknowledgment, Error Detection and Signalling. The MAC sublayer are supervised by a management entity called Fault Confinement which is self-checking mechanism for distinguishing short disturbances from permanent failures. The LLC sublayer is concerned with Message Filtering, Overload Notification and Recovery Management.

Explain RS-422 and draw a typical RS-422 application circuit.

The RS-422 standard specifies data rates up to 10 Mbps and line lengths of up to 4000 feet. The RS-485 Standard permits a balanced transmission line to be shared in a party line or multidrop mode. As many as 32 driver/receiver pairs can share a multidrop network. Many characteristics of the drivers and receivers are the same as RS-422. The range of the common mode voltage Vcm that the driver and receiver can tolerate is expanded to +12 to -7 volts. Since the driver can be disconnected or tristated from the line, it must withstand this common mode voltage range while in the tristate condition. Some RS-422 drivers, even with tristate capability, will not withstand the full Vcm voltage range of +12 to -7 volts. Figure 2 shows a typical RS-422 interface circuit. Although an RS-485 circuit may appear similar, the main difference is in the bus architecture. Figure 3 shows a typical RS-485 application circuit.

Which regulator is usually best suited for AC-powerd applications and why?

The Standard regulator is usually best for AC-powered applications, where the low cost and high load current make it the ideal choice. In AC-powered applications, the voltage across the regulator is usually at least 3V or more, so dropout voltage is not critical. Interestingly, in this type of application (where the voltage drop across the regulator is > 3V) Standard regulators are actually more efficient than LDO types (because the Standard has much less internal power dissipation due to ground pin current).

VMEbus basics?

The VMEbus is a 32-bit bus that is widely used worldwide in industrial, commercial and military applications. An abundance of VMEbus cards are available to perform a wide range of tasks, from digital image processing to disk controllers. The VMEbus supports multiple bus masters and high data transfer rates. Most VMEbus cards are configured via a combination of hardware jumpers, card-specific software configuration, and setting parameters in non-volatile memory. A VMEbus chassis consists of a card cage with 1 - 21 slots, a backplane with two connectors and, normally, five jumpers per slot. The slots are numbered from 1 - 21. Slot 1 is the System Controller slot. Cards with different functions are inserted in the slots to form a customized VMEbus chassis.

Draw a bdirectional RS-422 interface.

There is a wide variety of RS-422 interface chips available. Figure 9-11 shows a simple RS-422 bidirectional interface implemented using two Maxim MAX3488s. The Tx and Rx pairs of each MAX3488 are connected to UARTs within each embedded system, just as we did with RS-232C.

Explain Bus values (CAN):

The bus can have one of two complementary logical values: 'dominant' or 'recessive'. During simultaneous transmission of 'dominant' and 'recessive' bits, the resulting bus value will be 'dominant'. For example, in case of a wired-AND implementation of the bus, the 'dominant' level would be represented by a logical '0' and the 'recessive' level by a logical '1'. Physical states (e.g. electrical voltage, light) that represent the logical levels are not given in this specification.

Explain Single Channel (CAN):

The bus consists of a single channel that carries bits. From this data resynchronization information can be derived. The way in which this channel is implemented is not fixed in this specification. E.g. single wire (plus ground), two differential wires, optical fibres, etc.

Describe pipelining

The computer does three tings for each clock cycle: 1. Fetch new instruction 2. Decode next instruction 3. Execute one instruction

Draw the QUASI LOW-DROPOUT REGULATOR (QUASI-LDO). What is the dropout voltage, ground pin current and the load current?

The dropout voltage for the quasi-LDO is higher than the LDO, but lower than the Standard regulator. The ground pin current of the quasi-LDO is fairly low (usually less than 10mA for full rated current) which is as good as the Standard regulator.

Draw the the STANDARD (NPN) REGULATOR (STD). What is the dropout voltage, ground pin current and the load current?

The dropout voltage of the Standard regulator is the highest (worst). The ground pin current of the Standard regulator is the lowest (best)

What is the single most important difference between LDO, QUASI-LDO and STD regulators?

The dropout voltage, which is defined as the minimum voltage drop required across the regulator to maintain output voltage regulation. A critical point to be considered is that the linear regulator that operates with the smallest voltage across it dissipates the least internal power and has the highest efficiency. The LDO requires the least voltage across it, while the Standard regulator requires the most.

There are two methods of tristating an RS-485 driver. What are they?

The first method is to use a control line, often the RTS handshake line, to enable and disable the driver. This requires that the host software raise the RTS line before beginning a transmission to enable the driver, then lower the RTS line after the completion of the transmission. Since only a single RS-485 driver can be enabled on a network at one time it is important that the driver is disabled as quickly as possible after transmission to avoid two drivers trying to control the lines simultaneously, a condition called line contention. Under some operating systems it can be difficult to lower RTS in a timely manner and this method of driver control should be avoided altogether. The second method of RS-485 driver control we refer to as Automatic Send Data Control. This type of control involves special circuitry that senses when data is being transmitted and automatically enables the driver as well as disabling the driver within one character length of the end of transmission. This is the preferred method of driver control since it reduces software overhead and the number of potential pitfalls for the programmer.

What do we mean when we say that a machine is coarsely grained or finely grained?

The grain of the computer is defined as the number of processing elements within the machine. A coarsely grained machine has relatively few processors, whereas a finely grained machine may have tens of thousands of processing elements. Typically, the processing elements of a finely grained machine are much less powerful than those of a coarsely grained computer. The processing power is achieved through the brute- force approach of having such a large number of processing elements.

Whats the difference between Standard frames and Extended frames? (CAN)

There are two different formats which differ in the length of the IDENTIFIER field: Frames with the number of 11 bit IDENTIFIER are denoted Standard Frames. In contrast, frames containing 29 bit IDENTIFIER are denoted Extended Frames.

What is the second important difference between LDO, QUASI-LDO and STD regulators?

The ground pin current required by the regulator when driving rated load current. The Standard regulator has the lowest ground pin current, while the LDO generally has the highest (differences between the types is detailed in the following sections). Increased ground pin current is undesirable since it is "wasted" current, in that it must be supplied by the source but does not power the load.

Which of the three regulators LDO, QUASI-LDO and STD are best suited for battery-powered applications and why?

The lower dropout voltage is the reason LDO regulators dominate battery-powered applications, since they maximize the utilization of the available input voltage and can operate with higher efficiency. The LDO regulator is best suited for battery-powered applications, because the lower dropout voltage translates directly into cost savings by reducing the number of battery cells required to provide a regulated output voltage. If the input-output voltage differential is low (like 1V to 2V) the LDO is more efficient than a Standard regulator because of reduced power dissipation resulting from the load current multiplied times the input-output voltage differential.

Explain the buck regulator shortly

The most commonly used switching converter is the Buck, which is used to down-convert a DC voltage to a lower DC voltage of the same polarity. This is essential in systems that use distributed power rails (like 24V to 48V), which must be locally converted to 15V, 12V or 5V with very little power loss. The Buck converter uses a transistor as a switch that alternately connects and disconnects the input voltage to an inductor

What are MIMD computers MIMD computers

The other major form of parallel machine is the Multiple-Instruction Multiple-Data (MIMD) computer. These machines are typically coarsely grained collections of semi-autonomous processors, each with their own local memory and local programs. An algorithm being executed on an MIMD computer is typically broken up into a series of smaller sub-problems, each executed on a processor of the MIMD machine. By giving each processing element in the MIMD machine identical programs to execute, the MIMD machine may be treated as an SIMD computer. The grain of an MIMD computer is much less than that of an SIMD machine. MIMD computers tend to use a smaller number of very powerful processors, rather than a large number of less powerful ones.

Why do we use decoupling capacitors?

The principle of keeping current loops small applies as much to power lines within a system as it does to signal lines. However, keeping the loop area small for power is difficult. Power must be distributed throughout the circuit, and to effectively route this throughout a PCB, and keep the loop area small, is very difficult. The power lines can therefore be susceptible to noise, and this can cause major problems to the circuit. The solution is to provide a path to ground for any noise present in the power supply. This should be done locally for each component in the circuit. It is achieved by adding a decoupling capacitor between power and ground for each integrated circuit. The capacitor decouples the noise from the power source and provides a path to ground for it. In this way, noise is removed from the power supply, and the chips have a constant and clean voltage source. The decoupling capacitors should be placed as close as possible to the power pins of the devices. Surface-mount capacitors have very low inductance connections, and so are preferable. Ceramic capacitors are normally used for decoupling capacitors due to their low resistance. The capacitor has the added advantage of acting as a current source for the device when the device must switch its outputs or internal state. As such, it represents a current source with a much smaller loop area. Generally, the circuit board will be decoupled by a large (22-100 uF, say) electrolytic or tantalum capacitor placed near the power input, and each integrated circuit will be separately decoupled by 10 nF ceramic capacitors. Multiple decoupling capacitors, one for each power pin, improve the situation. You need to ensure that all frequencies that may affect the circuit have a low impedance path to ground. To this end, several capacitors (100 nF, 10 nF, and 100 pF) can be used to decouple a wide range of frequencies and thereby remove noise from the power-supply circuits. You can never have enough decoupling capacitors (within reason). Additionally, an onboard voltage regulator can provide a degree of isolation between your circuit and the external power supply. Every component should have a decoupling capacitor for every powersupply pin. This is important. Leaving them off is a good way to ensure that your computer will be unreliable.

Why is the quiesent (idling) current important for regulators?

The quiescent current that a part draws from the source when idling (either shut down or not delivering significant amounts of load current) can be of critical importance in battery-powered applications. In some applications, a regulator may spend most of its life shut off (in standby mode) and only supply load current when a main regulator fails. In these cases, the quiescent current determines the battery life. Many of the new LDO regulators are optimized for low quiescent current (like 75 to 150 μA), and provide significant improvement over typical regulators which draw several milliamps.

What is quadrature encoding?

The rate at which the pulses arrive gives the motor's speed, and the order in which they arrive shows the direction. This is known as quadrature encoding.

How many conductors does the RS-485 and RS-422 need?

The signal ground conductor is often overlooked when ordering cable. An extra twisted pair must be specified to have enough conductors to run a signal ground. A two-wire system then requires two twisted pair, and a four-wire system requires three twisted pair.

How many devices does I2C support?

The software limiting factor is the size of the address used for the slaves 7-bit, 8-bit, or 10-bit. They support 127, 255, and 1023 devices respectively.

In any transfer of data over a potentially noisy medium (such as a serial cable), the possibility of errors exists. To detect such errors, many serial systems implement parity as a simple check for the validity of the data. How does a parity check work? Give an example.

There are several types of parity, the main two being even parity and odd parity. In any byte of data, there is either an even number of "1" bits or an odd number of "1" bits. An extra bit (the parity bit) is added to the byte to make the number of "1" bits even (even parity) or odd (odd parity). For successful transmission, both the receiver and transmitter must be set for the same type of parity generation. There is no protocol for establishing common parity settings between UARTs; it must be done manually at either end. So for the binary sequence %01000000, the parity bit would be "1" for even parity and "0" for odd parity. Similarly, for %11111111, the parity bit would be "0" if we were using even parity and "1" if we had odd parity. The generation and detection of parity is done automatically by dedicated hardware within the UART. It's not something you explicitly have to calculate. You do have to make sure your UART is set to the correct type of parity generation; otherwise, it will not know how to process the parity information accordingly. The parity bit is checked at the receiving end against the data to check whether any of the bits were corrupted during transmission. Say we sent %01000000. If our UART was set to even parity, the calculated parity bit from %01000000 would be 1. Now, let's say this transmission was corrupted along the way, such that what was actually received was %01000001. The receiver would calculate the even parity of the byte to be 0. In comparing this to the received parity bit of 1, a parity error would be detected, and the receiver would take appropriate action (such as requesting that the byte be sent again). Note that how parity errors are handled is the responsibility of the programmer. The UART itself takes no action beyond flagging the error. It is up to the software to implement appropriate error handling.

What is a Four Wire Master-Slave Systems (RS-485/RS-422 )

This configuration reduces software complexity at the host since the driver and receiver are always enabled, at the expense of installing two extra conductors in the system. The Master node simply prefixes commands with the appropriate address of the slave. There is no data echo or turn around delays to consider. Since each of the slave transmitters share the same pair of wires, care must be taken that the master never requests data from multiple nodes simultaneously or data collisions will result.

Explain Sleep Mode / Wake-up (CAN):

To reduce the system's power consumption, a CAN-device may be set into sleep mode without any internal activity and with disconnected bus drivers. The sleep mode is finished with a wake-up by any bus activity or by internal conditions of the system. On wake-up, the internal activity is restarted, although the MAC sublayer will be waiting for the system's oscillator to stabilize and it will then wait until it has synchronized itself to the bus activity (by checking for eleven consecutive 'recessive' bits), before the bus drivers are set to "on-bus" again.

What four different packet types does USB have?

Token packets, Data packets, Handshake packets and start of frame packets USB has four different packet types. Token packets indicate the type of transaction to follow, data packets contain the payload, handshake packets are used for acknowledging data or reporting errors and start of frame packets indicate the start of a new frame.

What is a Two Wire Master-Slave Systems (RS-485/RS-422 )

Two wire configurations add a small amount of complexity to the system. The RS-485 driver must be tristated when not in use to allow other nodes to use the shared pair of wires. The time delay between the end of a transmission and the tristate condition becomes a very important parameter in this type system. If a slave attempts to reply before the master has tristated the line, a collision will occur and data will be lost. The system designer must know the response time or turn around delay of each of the slave nodes and assure that the master will tristate its driver within that amount of time. B&B Electronics' Automatic Send Data control circuits tristate the driver within one character length of the end of a transmission.

In short, how does a I2C bus work?

Two wires, serial data (SDA) and serial clock (SCL), carry information between the devices connected to the bus. Each device is recognized by a unique address (whether it is a microcontroller, LCD driver, memory or keyboard interface) and can operate as either a transmitter or receiver, depending on the function of the device. An LCD driver may be only a receiver, whereas a memory can both receive and transmit data. In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave. The I2C-bus is a multi-master bus. This means that more than one device capable of controlling the bus can be connected to it. As masters are usually microcontrollers.

What is the output voltage precision of linear regulators?

Typical linear regulators usually have an output voltage specification that guarantees the regulated output will be within 5% of nominal. This level of accuracy is adequate for most applications. There are many new regulators which have tighter output tolerances (better than 2% is common), achieved through the use of a laser-trim process. Also, many of the new regulators have separate output specifications that cover room temperature/full operating temperature range, and full-load/light-load conditions.

What are the pin-functions in the USB?

USB as its name would suggest is a serial bus. It uses 4 shielded wires of which two are power (+5v & GND). The remaining two are twisted pair differential data signals. It uses a NRZI (Non Return to Zero Invert) encoding scheme to send data with a sync field to synchronise the host and receiver clocks.

How does RS-422 work? Draw a connection.

Unlike RS-232C, which is referenced to local ground, RS-422 uses the difference between two lines, known as a twisted pair or a differential pair, to represent the logic level. Thus, RS-422 is a balanced transmission, or, in other words, it is not referenced to local ground. Any noise or interference will affect both wires of the twisted pair, but the difference between them will be less affected. This is known as common-mode rejection. RS-422 can therefore carry data over longer distances and at higher rates with greater noise immunity than RS-232C. RS-422 can support data transmission over cable lengths of up to 1,200 meters (approximately 4,000 feet).

What is SPI, and how does it work? Draw a basic SPI Interface.

Unlike a standard serial port, SPI (Serial Peripheral Interface ) is a synchronous protocol in which all transmissions are referenced to a common clock, generated by the master (processor). The receiving peripheral (slave) uses the clock to synchronize its acquisition of the serial bit stream. Many chips may be connected to the same SPI interface of a master. A master selects a slave to receive by asserting the slave's chip select input. A peripheral that is not selected will not take part in a SPI transfer. SPI uses four main signals: Master Out Slave In (MOSI), Master In Slave Out (MISO), Serial CLocK (SCLK or SCK) and Chip Select (bar{CS}) for the peripheral. Some processors have a dedicated chip select for SPI interfacing called Slave Select (bar{SS}). MOSI is generated by the master and is received by the slave. On some chips, MOSI is labeled simply as Serial In (SI) or Serial Data In (SDI). MISO is produced by the slave, but its generation is controlled by the master. MISO is sometimes known as Serial Out (SO) or Serial Data Out (SDO) on some chips. The chip select to the peripheral is normally generated by simply using a spare I/O pin of the master. Figure 7-1 shows a microprocessor interfaced to a peripheral using SPI.

How many devices can be connected to any one USB bus at any one given time

Up to 127 devices can be connected to any one USB bus at any one given time

Explain how differential data transmission works

WHY USE DIFFERENTIAL DATA TRANSMISSION? The main reason why RS-485 can communicate over long distances is the use of differential or balanced lines. A communication channel requires a dedicated pair of signal lines to exchange information. The voltage on one line equals the inverse of the voltage on the other line. TIA/EIA-485-A designates the two lines in this differential pair as A and B. Line A is more positive than Line B (VOA > VOB) on the driver output if a logic high is received on the input of the transmitter (DI = 1). If a logic low is received on the input of the transmitter (DI = 0), the transmitter causes Line B to be more positive than Line A (VOB > VOA). See Figure 1. If Line A is more positive than line B (VIA − VIB > 200 mV) on the input of the receiver, the receiver output is a logic high (RO = 1). If Line B is more positive than Line A (VIB − VIA > 200 mV) on the input of the receiver, the receiver output is a logic low (RO = 0). Figure 1 shows that a differential signaling interface circuit consists of a driver with differential outputs and a receiver with differential inputs. This circuit has increased noise performance because the noise coupling into the system is equal on both signals. One signal emits the opposite of the other signal and electromagnetic fields cancel each other. This reduces the electromagnetic interference (EMI) of the system.

How does the CAN protocol handle a situation if it starts detecting in messages that are actually incorrect?

When detecting an error, the node will transmit an error-flag. If this happens multiple times, the "Receive Error Counter" will fill up, and the node will eventually be set in "error passive mode"

Explain Multimaster (CAN):

When the bus is free any unit may start to transmit a message. The unit with the message of higher priority to be transmitted gains bus access.

Explain Arbitration (CAN):

Whenever the bus is free, any unit may start to transmit a message. If 2 or more units start transmitting messages at the same time, the bus access conflict is resolved by bitwise arbitration using the IDENTIFIER. The mechanism of arbitration guarantees that neither information nor time is lost. If a DATA FRAME and a REMOTE FRAME with the same IDENTIFIER are initiated at the same time, the DATA FRAME prevails over the REMOTE FRAME. During arbitration every transmitter compares the level of the bit transmitted with the level that is monitored on the bus. If these levels are equal the unit may continue to send. When a 'recessive' level is sent and a 'dominant' level is monitored (see Bus Values), the unit has lost arbitration and must withdraw without sending one more bit.

(USB) What are pipes, and what two pipes are there?

While the device sends and receives data on a series of endpoints, the client software transfers data through pipes. A pipe is a logical connection between the host and endpoint(s). Pipes will also have a set of parameters associated with them such as how much bandwidth is allocated to it, what transfer type (Control, Bulk, Iso or Interrupt) it uses, a direction of data flow and maximum packet/buffer sizes. For example the default pipe is a bi-directional pipe made up of endpoint zero in and endpoint zero out with a control transfer type. USB defines two types of pipes • Stream Pipes have no defined USB format, that is you can send any type of data down a stream pipe and can retrieve the data out the other end. Data flows sequentially and has a pre-defined direction, either in or out. Stream pipes will support bulk, isochronous and interrupt transfer types. Stream pipes can either be controlled by the host or device. • Message Pipes have a defined USB format. They are host controlled, which are initiated by a request sent from the host. Data is then transferred in the desired direction, dictated by the request. Therefore message pipes allow data to flow in both directions but will only support control transfers.

Can you daisy-chain SPI devices?

Yes. Some slaves support being daisy-chained together

Bluetooth

advertiser er en sensor som kan bli connectet til av en scanner Scanner er typisk en smarttelefon eller lignende, og kan initiate connection til advertisers Broadcaster er det samme som advertiser, bare den ikke kan bli connectet til Observer er det samme som scanner, bare den ikke kan initiate connections the short/long/short version :)))

I2C-bus terminology Arbitration

procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the winning message is not corrupted

I2C-bus terminology Synchronization

procedure to synchronize the clock signals of two or more devices

I2C-bus terminology Slave

the device addressed by a master

I2C-bus terminology Master

the device which initiates a transfer, generates clock signals and terminates a transfer

I2C-bus terminology Receiver

the device which receives data from the bus

I2C-bus terminology Transmitter

the device which sends data to the bus

Benefits of RS-485

• Long distance links—up to 4000 feet. • Bidirectional communications possible over a single pair of twisted cables. • Differential transmission increases noise immunity and decreases noise emissions. • Multiple drivers and receivers can be connected on the same bus. • Wide common-mode range allows for differences in ground potential between the driver and receiver. • TIA/EIA-485-A allow for data rates of up to 10 Mbps. Devices meeting the TIA/EIA-485-A specifications do not have to operate o

Define Open system, embedded system and deeply embedded system

• Open systems - General purpose computing - Purpose-loaded functions - Flexible, high performance, no limitations on energy • Embedded systems - Fixed-function, optimized, high/low performance - Part of larger system - Computer not the «purpose» of the system • Deeply embedded systems - Devices of a single purpose - Not «visible», highly optimized wrt. application - Typically sense -> process -> act