Computer Science 2150 Exam II

The FLOP

Clock speed should not be confused with overall CPU performance. There are many other factors that contribute to the throughput of a computer's assigned task. Which does Not contribute to the CPU's performance

Data hazards

Dependencies between instructions are not met due to the instructions being executed simultaneously

Structural hazards

Hardware cannot support all possible combinations of instructions

7 with an error margin of 0

If a pipeline has seven stages, what is the theoretical speedup possible as compared to a sequential processor

Control hazards

Occurs when executing a branch or jump instruction. If the branch is taken, any instruction fetched after the branch instruction are not useful

It contains both data and address lines, and has better overall performance

Of the two main types of buses, dedicated has what features

It contains both data and address lines, times shares and data lines, has fewer lines for the same application, and more complex control

Of the two main types of buses, multiplexed has what features

True

True/False There are two different methods of implementing the decoding control unit: hardwired control which is implemented using digital logic components and microprogrammed control where a small program is placed into ROM. In hardwired control, instruction machine code bit pattern in the IR is decoded by combinational logic. The decode output works with the control signals of the current system state to produce a new set of control signals. The control signals are routed to registers, the datapath, and the ALU to execute the specific instruction

False

True/False A least recently used (LRU) algorithm keeps track of the last time that a block was assessed and evicts the blocks that was used most recently by the CPU

False

True/False A shorter program will always execute faster

True

True/False Amdahl's Law gives us a way to estimate the performance improvement from an updated component. The performance is most improved when the most used component is improved

True

True/False An entire block of data is copied to cache after a hit in memory because the principal of locality tells us that once a byte is accessed, it is likely that a nearby data element will be needed soon. (The simplest replacement algorithm is direct mapped block)

False

True/False An interrupt is a mechanism by which other modules may interrupt the normal sequence of processing. An interrupt is planned, but an unscheduled event. Typically, the interrupt is of lower priority than routine program execution

True

True/False As compared to polling techniques, an interrupt is a time efficient method of responding to an external stimulus. When an external event occurs, interrupt specific processing is executed

True

True/False Big endian machines store the most significant byte first (at the lower address)

True

True/False CISC systems improve performance by reducing the number of instructions per program

True

True/False Cache replacement policies must take into account dirty blocks, those blocks that have been updated while they were in the cache. Write through updates cache and main memory simultaneously on every write

True

True/False Channel I/O is distinguished from DMA by the intelligence of the in/out Processors (IOPs). The IOP negotiates protocols, issues device commands, translates storage coding to memory coding and can transfer entire files and groups of files independent of the host CPU

True

True/False DMA runs at a higher priority and steals memory cycles from the CPU. During a transfer the CPU is bypassed

False

True/False Dynamic RAM is "cheap" memory owing to its simple design. DRAM enjoys high bit density -- that is, more memory capacity per unit area as compared to Static RAM. DRAM is also faster (lower access time) as compared to SRAM because memory cell refresh is not required

True

True/False Each newer language generation presents problem solving tools that are closer to how people think and farther from how the machine implements the solution

True

True/False Flynn's Taxonomy takes into consideration the number of processors and the number of data paths incorporated into an architecture

True

True/False In GPR architecture, registers are used instead of memory. This results in longer (wider) instructions. Most systems today use the GPR approach. Operand access from registers is much faster than memory access

True

True/False In Redundant Array of Independent Disks (RAID), data is stored across many disks, with extra disks added to the array to provide error correction (redundancy) A higher RAID level does not mean a better RAID level

True

True/False In a stack architecture, instructions and operands are implicitly taken from the stack

True

True/False In an accumulator architecture, one operand of a binary operation is implicitly in the accumulator. The other operand is in memory, creating considerable bus traffic

True

True/False In direct mapped cache block replacement technique, a cache consisting of N blocks of cache and X blocks of main memory maps to cache block Y = X mod N. This provides for a fixed cache location for a given block; however, multiple blocks within main memory may map to the same block within cache

True

True/False In memory-mapped I/O, devices and main memory share the same address space. Each I/O device has its own reserved block of memory. Memory-mapped I/O therefore looks just like a memory access from the point of view of the CPU

False

True/False Java programs execute within a virtual machine, the JVM. Because the JVM performs so many tasks at run time, its performance surpasses the performance of a traditional compiled language

True

True/False Low cost is the major advantage of hard disks; however, their limitations include: they are very slow compared to main memory, they are fragile, and the moving parts wear out

True

True/False Many operating systems provide protection environments that isolate processes, or groups of processes from each other. Three common approaches to established protected environments are virtual machines, subsystems and partitions

False

True/False Memory addresses consists of two parts: the memory bank select address and the specific memory address within a given memory chip. With high-order interleaving, the low order bits of the address specify which memory bank contains the address of interest

True

True/False Memory hierarchy involves registers, cache, main memory, and virtual memory. Registers are storage locations near or on the processor itself

True

True/False Parallel processing is capable of economically increasing system throughput while providing better fault tolerance. BUT keep in mind that an n-fold increase in processing power does not mean an n-fold increase in throughput

True

True/False Perceptrons are trained by use of supervised or unsupervised learning. Unsupervised learning does not provide correct results during training. The network adapts solely in response to inputs, learning to recognize patterns and structures in the input sets

True

True/False Pipelining does not improve the latency of a single program stem; however, pipelining improves the entire throughput of a program

True

True/False Pipelining theoretically reduces the clocks per instruction (CPI) to an ideal value of one. The ideal value is hard to achieve because of real world pipeline hazards

True

True/False Process management lie at the heart of operating system services. the operating system creates processes, scheduling their access to resources, deletes processes, and deallocates resources that were allocated during process execution

True

True/False RAM is volatile. That is, it loses its memory when power is removed. It is used extensively within a computer system for main memory and stack hosting

True

True/False ROM is non-volatile. That is, it retains contents even during power failure. It is used permanent storage applications such as microprogramming.

False

True/False Registers hold data that can be readily accessed by the CPU. A register is typically implemented using D flops. Data stored in main memory typically has a shorter access time than data stored in a CPU register

True

True/False Solid State Drive (SSD) access time and transfer rates are significantly fatser than magnetic disk, but much slower than onboard main memory (RAM). The primary advantages of SSD over hard drives is the are no moving parts

True

True/False Stack machines use one - and zero-operand instructions. PUSH and POP stack operations involve only the stack's top element

True

True/False The arithmetic logic unit carries out logical and arithmetic operations as directed by the control unit

False

True/False The cache memory is to speed up accesses by storing recently used data closer to the CPU, instead of main memory. The cache memory is smaller than main memory and its access time is a fraction of that of main memory (much faster). The cost to a bit in cache memory is much less expensive than main memory

True

True/False The goal of a designer is to balance the pipeline stages because unbalanced pipe stage reduces speed up

True

True/False The kernel performs the following: Scheduling, Synchronization, memory management, interrupt handling and security

False

True/False The machine cycle is the time required to move an instruction one step further in the pipeline. The machine cycle is the time an instruction spends in the fastest pipe stage

True

True/False The two principal parts of the CPU are the datapath and the control unit. The datapath consists of an arithmatic logic unit and registers. The CPU performs sequenced operations according to signals provided by its control unit

True

True/False The underlying philosophy of RISC machines is that a system is better able to manage program execution when the program consists of only a few different instructions that are the same length and require the same number of clock cycles to decode and execute

True

True/False There are two different methods of implementing the decoding control unit: hardwired control which is implemented using digital logic components and microprogrammed control where a small program is placed into ROM. In microprogrammed control, the instruction microcode produces control signal changes. The resulting microprogram is stored in firmware. This extra level of instruction interpretation is what makes microprogrammed control slower than hardwired control

True

True/False There are two different methods of implementing the decoding control unit: hardwired control which is implemented using digital logic components and microprogrammed control where a small program is placed into ROM. The resulting control signal pattern is the same regardless of which control scheme is implemented

True

True/False Virtual memory enhances performance by providing greater memory capacity, without the expense of adding main memory. A portion of a disk drive serves as an extension of main memory

True

True/False Virtual memory is memory that appears to exist as main storage (RAM) although most of it is supported by data held in secondary storage (hard drive). This technique extends the address space from RAM to the hard drive

Contains the machine code instruction

What does the IR register do

Holds the memory address constant during memory operation

What does the MAR register do

Storage register for data coming in and out of memory

What does the MBR register do

Contains the next instruction to be executed

What does the PC register do

Short term

What type of scheduler selects which process should be executed next by the CPU

Address bus

Which bus width determines the maximum memory capacity of the system

Data bus

Which bus width determines the range of integers that may be stored in a computer