Digital Design & Computer Architecture

Resistor-Transistor Logic (RTL)

Uses nMOS transistors to pull the gate output LOW and a weak resistor to pull the output HIGH when none of the paths to ground are active.

Most Significant Bit (msb) & Least Significant Bit (lsb) Most Significant Byte (MSB) & Least Significant Byte (LSB)

msb = leftmost bit, lsb = rightmost bit MSB = leftmost byte, LSB = rightmost byte

Gated Clock

A clock signal with an additional enable input.

State variables

A set of bits that contain all the information about the past necessary to explain the future behavior of the circuit.

Flip-Flop

The simplest synchronous sequential circuit. It has one input, D, one clock, CLK, one output, Q, and two states, {0, 1}.

Circuit Schematic Nomenclature

- Inputs are on the left (or top) side of a schematic. - Outputs are on the right (or bottom) side of a schematic. - Whenever possible, gates should flow from left to right. - Straight wires are better to use than wires with multiple corners. - Wires always connect at a T junction. - A dot where wires cross indicates a connection between the wires. - Wires crossing without a dot make no connection.

Synchronous Sequential Circuit Composition

- Every circuit element is either a register or a combinational circuit. - At least one circuit element is a register. - All registers receive the same clock signal. - Every cyclic path contains at least one register.

FSM Design Procedure

- Identify inputs and outputs - Sketch state transition diagram - Write state transition table and output table - Moore FSM: write separate tables - Mealy FSM: write combined state transition and output table - Select state encodings - Rewrite state transition table and output table with state encodings - Write Boolean equations for next state and output logic - Sketch the circuit schematic

Boolean Terminology

- The complement of a variable is its inverse. - The variable or its complement are called a literal. - The AND of one or more literals is called a product or implicant. - The OR of one or more literals is called a sum. - A minterm is a product involving all of the inputs of the functions. - A maxterm is a sum involving all of the inputs of the function. - A prime implicant cannot be combined with other implicants to form a new implicant.

Truth Table Nomenclature

0 = LOW 1 = HIGH X = Dont care Z = Floating

The 8 Great ideas in Computer Architecture

1. Design for Moore's Law 2. Use Abstraction to Simplify Design 3. Make the Common Case Fast 4. Performance via Parallelism 5. Performance via Pipelining 6. Performance via Prediction 7. Hierarchy of Memories 8. Dependability via Redundancy

Nibble

4 bits or half a byte. Represented using one hexadecimal digit.

Hexadecimal number

4 bits together can represent 16 different values (2^4 = 16), so a single hexadecimal value can represent all these possibilities because hexadecimal is base-16. Each place value has a weight of 16.

Complementary Metal Oxide Semiconductor Logic (CMOS Logic)

A circuit that uses complementary pairs of p-channel and n-channel MOSFETs together to perform logic functions.

Sequential Circuit

A circuit whose outputs depend on both the current and previous values of the inputs, the output is determined by the input sequence. Contains memory.

Combinational Circuit

A circuit whose outputs only depend on the current value of the inputs to compute the output. Memoryless.

Unstable / Astable

A circuit with no stable states.

Byte

8 bits. Represented using two hexadecimal digits.

Product-of-sums Form

A Boolean equation can be created for each row of a truth table that corresponds to a max-term that is FALSE for that row.

Sum-of-products Form

A Boolean equation for any truth table can be created by summing each of the minterms for which the output, Y, is TRUE.

Enabled Flip-Flop

A D Flip-Flop with an additional input called ENABLE (EN) that determines whether data is loaded on the clock edge. When EN is TRUE, the enabled flip-flop behaves like an ordinary D flip-flop. When EN is FALSE, the enabled flip-flop ignores the clock and retains its state. It is useful when we wish to load a new value into a flip-flop only some of the time, rather than on every clock edge.

Resettable Flip-Flop

A D Flip-Flop with an additional input called RESET. When RESET is FALSE, the resettable flip-flop behaves like an ordinary D flip-flop. When RESET is TRUE, the resettable flip-flop ignores D and resets the output to 0. It is useful when we want to force a known state into all the flip-flops in a system when we first turn it on. These flip-flops may be synchronously or asynchronously resettable. Synchronously resettable flip-flops reset themselves only on the rising edge of the clock. Asynchronously resettable flip-flops reset themselves as soon as RESET becomes TRUE, independent of the clock.

Finite State Machines (FSMs)

A Synchronous sequential circuit with k registers can be in one of a finite number (2^k) of unique states. An FSM has M inputs, N outputs, and k bits of state. It also receives a clock and, optionally, a reset signal. An FSM consists of two blocks of combinational logic, next state logic and output logic, and a register that stores the state. Finite state machines provide a systematic way to design synchronous sequential circuits given a functional specification.

Hexadecimal

A base-16 number system that uses sixteen distinct symbols 0-9 and A-F to represent numbers from 0 to 15.

Contention

A circuit is being driven to both HIGH and LOW simultaneously. Can also be dangerous because large amounts of power flow between the competing gates, generating heat and possibly causing damage. Indicated by an X on the circuit schematic diagram.

Multiplexer (mux)

A combinational circuit that chooses an output from among several possible inputs based on the value of a select or control signal.

Bit

A contraction of "Binary Digit". A bit is the single unit of information in a computer, typically represented as a 0 or 1.

Decoder

A control circuit that has N inputs and 2^(N) outputs. It asserts exactly one of its outputs depending on the input combination.

Logic Gate

A digital electronic circuit that performs a Boolean algebraic function by taking one or more binary inputs and producing a binary output. A truth table lists the inputs and outputs and a Boolean equation can list the logic gate's function mathematically.

Transistor-Transistor Logic (TTL)

A family of digital logic devices whose basic element is the bipolar junction transistor.

Timing Diagram

A graph that shows the transient response of a circuit when an input changes. The transition from LOW to HIGH is called the rising edge, and the transition from HIGH to LOW is called the falling edge. Delay is measured at the half-points on the rising edge of the signal.

Two's complement notation

A method of representing negative numbers in the binary system. Similar to signed binary, but instead of the msb being a positive or negative sign the msb has a negative weight. Positive numbers are identical to signed binary up to the sign bit, in order to find the negative or complement of the positive number do the following: 1. Invert the bits. 2. Add 1 to the result. 3. Ignore the carry.

D Latch

A more advanced version of the SR Latch that includes a data input (D) that controls what the state of the circuit should be and a clock input (CLK) that controls when the state should change. When CLK = 0, Q retains its old value, while when CLK = 1, Q = D. The latch is said to be transparent when CLK = 1, and opaque when CLK = 0. The D Latch is also referred to as a transparent or level-sensitive latch. The D latch updates its state continuously while CLK = 1.

Circuit

A network that processes discrete valued variables. It will have one or more input and output terminals and will include a functional specification and timing specification. A circuit is composed of nodes and elements. Circuits are classified as combinational or sequential.

Binary number

A number composed of just 0s and 1s, also known as a base-2 number. Represents 2^N possible values.

SR Latch

A simple bistable sequential circuit composed of two cross-coupled NOR (or NAND) gates. It has two inputs (S & R) and two outputs (Q & ￢Q). The state of the circuit is controlled through the set and reset inputs, which control the output, Q and ￢Q. The outputs, Q and ￢Q are complementary and have opposite values. Because of this the state of the circuit is stored in a single variable, Q.

Metal Oxide Semiconductor Field Effect Transistor (MOSFET)

A small electronic device used in a circuit as an amplifier or switch. Switch opens or closes depending on the voltage at the gate. Comes in two types, pMOS and nMOS.

Metastable State

A state in which outputs are approximately half-way between 0 and 1.

Cross-coupled

A symmetrical circuit whose outputs are fed into the adjacent gates' input.

Logic Level

A voltage of a specified value that is used to represent either a binary 1 or binary 0.

Register

An N-bit register is a bank of N flip-flops that share a common clock input. All bits of the register are updated at the same time.

Functional Specification

Describes relationship between input and output. Typically expressed as a truth table or boolean equation.

Hierarchy

Involves dividing a system into modules, then further sub-dividing each of these modules until the pieces are easy to understand.

Unsigned binary

Binary that represents positive numbers only.

Signed / magnitude binary

Binary with a positive or negative sign. The sign is indicated by the msb, 1 = negative, 0 = positive.

Timing Specification

Describes the delays between inputs changing and outputs responding, typically consisting of upper and lower bounds on the delay from input to output.

Cyclic Paths

Circuit output is fed directly back into the inputs.

Floating / High Impedance / High-Z

Circuit value is neither HIGH or LOW. The value of the node is irrelevant to circuit operation, its logic level is irrelevant so long as the node is not forced into any state. Indicated by a Z on the circuit schematic diagram.

Timing Specification of Synchronous Sequential Circuit

Consists of an upper bound, tpcq, and a lower bound, tccq, on the time from the rising edge of the clock until the output changes, as well as setup and hold times, tsetup and thold, that indicate when the inputs must be stable relative to the rising edge of the clock.

Circuit State

Current State = state of the circuit in the present time. Next State = state of the circuit on the next clock edge. We call the current state variable S and the next state variable S′.

Abstraction

Details are hidden when they are not important. Allows for easier understanding at a higher level.

Combinational Composition

Dictates how large combinational circuits can be built from smaller combinational circuit elements. A circuit is combinational if it consists of interconnected circuit elements such that: - Every circuit element is itself combinational. - Every node of the circuit is either designated as an input to the circuit or connects to exactly one output terminal of a circuit element. - The circuit contains no cyclic paths: every path through the circuit visits each circuit node at most once.

Dynamic Power Consumption

Dynamic power is the power used to charge capacitance as signals change between 0 and 1.

State

Everything about the prior inputs to the circuit; necessary to predict its future behavior. Typically stored as just 1 bit.

Karnaugh Map (k-maps)

Graphical method for simplifying Boolean equations. The rules for finding a minimized equation from a Karnaugh-map are as follows: - Use the fewest circles necessary to cover all the 1's. - All the squares in each circle must contain 1's. - Each circle must span a rectangular block that is a power of 2 (i.e., 1, 2, or 4) squares in each direction. - Each circle should be as large as possible. - A circle may wrap around the edges of the K-map. - A 1 in a K-map may be circled multiple times if doing so allows fewer circles to be used.

Tri-State Buffer

Has three possible output states: HIGH (1), LOW (0), and floating (Z). When the enable is TRUE, the tristate buffer acts as a simple buffer, transferring the input value to the output. When the enable is FALSE, the output is allowed to float (Z).

Static Discipline

If given logically valid inputs, every circuit element will produce logically valid outputs.

Conduction Complements

In a properly functioning logic gate, one of the networks should be ON and the other OFF at any given time, so that the output is pulled HIGH or LOW but not shorted or floating. We can guarantee this by using the rule of conduction complements. When nMOS transistors are in series, the pMOS transistors must be in parallel. When nMOS transistors are in parallel, the pMOS transistors must be in series.

Multiplexer Logic

In general, a 2^(N) -input multiplexer can be programmed to perform any N-input logic function by applying 0's and 1's to the appropriate data inputs. Any 1 output logic function can be implemented with a multiplexer.

State Transition Table

Indicates for each state and input, what the next state, S′, should be.

Level Triggered

Input changes only when the CLK is HIGH or LOW.

Edge Triggered

Input changes only when the CLK is transitioning from LOW to HIGH or HIGH to LOW.

Kilobyte, Megabyte, Gigabyte, Terabyte, Petabyte, Exabyte

Kilobyte = 2^10 bytes ~ 10^3 Megabyte = 2^20 bytes ~ 10^6 Gigabyte = 2^30 bytes~ 10^9 Terabyte = 2^40 bytes ~ 10^12 Petabyte = 2^50 bytes ~ 10^15 Exabyte = 2^60 bytes ~ 10^18

Latch vs Flip-Flop

Latch = Bistable element without an edge-triggered clock. Flip-Flop = A bistable element with an edge triggered clock input.

Settable Flip-Flop

Loads a 1 into the flip-flop when SET is asserted. Comes in synchronous and asynchronous flavors.

Logic Families

Logic gates are grouped into logic families such that all gates in a logic family obey the static discipline when used with other gates in the family.

Two-level logic

Logic in sum-of-products form. Named accordingly because it consists of literals connected to a level of AND gates connected to a level of OR gates.

NMOS Transistor

N-channel MOSFET transistor. Transistor remains ON while voltage is 1 at the gate.

Boolean Order of Operations

NOT, AND, OR

Moore machines

Outputs depend only on the current state of the machine.

PMOS Transistor

P-channel MOSFET transistor. Transistor remains ON while voltage is 0 at the gate.

Pseudo-nMOS Logic

Pseudo-nMOS logic replaces the slow stack of pMOS transistors with a single weak pMOS transistor that is always ON, often called a weak pull-up. The pMOS will pull the output up to HIGH only if all the nMOS transistors are OFF. If any of the nMOS transistors are ON they will overpower the weak pMOS and produce a logical 0.

Synchronous Sequential Circuit

Registers are inserted into the cyclic path of a sequential circuit to transform it into a collection of combinational logic and registers. The registers hold the state of the system, and they are synchronized to the clock. Race conditions common in asynchronous circuits are eliminated when applying these principles, assuming the clock is sufficiently slow and all registers can settle before the next clock edge. A sequential circuit has a finite set of discrete states {S0, S1, S2,...}. The rising edge of the clock indicates when state transitions should occur.

Regularity

Seeks uniformity among the modules. Common modules are reused many times, reducing the number of distinct modules that must be designed.

Modularity

States that the modules should have well-defined functions and interfaces, so that they connect together easily without unanticipated side effects.

Static Power Consumption

Static power is the power used even when signals do not change and the system is idle.

FSM Factoring

The act of breaking down a complex FSM into multiple smaller, simpler FSMs.

Discipline

The act of intentionally restricting design choices so that you can work more productively at a higher level of abstraction.

Word Size

The amount of bits which a computer operates reads at each instance. Word size is determined by the processors architecture. A 64 bit computer will read 64 bits of information at a time.

Noise Margin

The amount of noise that could be added to a worst-case output such that the signal can still be interpreted as a valid input. VOH > VIH > VOL > VIL

Element and Node

The element is the circuit itself while the node is a wire whose voltage conveys a discrete valued variable.

Voltage Driver Device (VDD)

The highest voltage in a system, typically comes from the power supply.

Critical path

The longest, and slowest path for an input to travel to the output.

Ground (GND)

The lowest voltage in a system.

Propagation delay (tpd)

The maximum time from when an input changes until the outputs reach their final value. The propagation delay of a combinational circuit is the sum of the propagation delays through each element on the critical path. Propagation delay increases linearly with chained inputs and logarithmically when inputs are hierarchical. Maximum delay from input to output

Contamination delay (tcd)

The minimum time from when an input changes until any output starts to change its value. The contamination delay is the sum of the contamination delays through each element on the short path. Minimum delay from input to output.

Mealy machines

The outputs depend on both the current state and the current inputs.

Circuit Bubble Pushing

The rules of circuit bubble pushing are: - Begin at the output of the circuit and work toward the inputs. - Push any bubbles on the final output back toward the inputs so that you can read an equation in terms of the output (for example, Y) instead of the complement of the output Y. Working backward, draw each gate in a form so that bubbles cancel. - If the current gate has an input bubble, draw the preceding gate with an output bubble. If the current gate does not have an input bubble, draw the preceding gate without an output bubble. - Bubbles can be added to the output of a gate and the input of the next gate without changing the function.

Short path

The shortest, and fastest path through the circuit.

DC Transfer Characteristics

The transfer characteristics of a gate describe the output voltage as a function of the input voltage when the input is changed slowly enough that the output can keep up.

Unity Gain Points

The typical place where logic levels are mapped onto analog circuits, typically where the slope of V(Y)/V(A) = -1 or 1 on a voltage transfer characteristic graph.

Logic Gate Bubble Pushing

The underlying rules for bubble pushing are: - Pushing bubbles backward (from the output) or forward (from the inputs) changes the body of the gate from AND to OR or vice versa. - Pushing a bubble from the output back to the inputs puts bubbles on all gate inputs. - Pushing bubbles on all gate inputs forward toward the output puts a bubble on the output.

State Encodings

The value of a state and its outputs. The two most common types of encoding are binary encoding, one-hot encoding and gray-codes.

D Flip-Flop

Two back-to-back D Latches controlled by a complementary clock. The first latch is called the leader and the second is called the follower. When CLK = 0, the leader is transparent and the follower is opaque. Therefore, whatever value was at D propagates through. When CLK = 1, the leader goes opaque and the follower becomes transparent. The value at the leader propagates through to Q, but the leader is cut off from D. A D flip-flop is also known as an edge-triggered flip-flop or a positive edge-triggered flip-flop.

Range of N-bit numbers

Unsigned: [0, 2^(N) - 1] Sign / Magnitude: [-2^(N-1) + 1, 2^(N-1) - 1] Two's Complement: [-2^(N-1), 2^(N-1) -1]

Binary Encoding

Uses a binary count to represent the state. N bits can represent 2^N states.

Glitches

When a single input transition causes multiple output transitions.

Sign Extension

When a two's complement number is extended to more bits, the sign bit must be copied into the most significant bit position in order for the number to stay valid.