Sequential Circuits

Two main types of sequential circuits based on the timing of their signals.

- A synchronous sequential circuit is a system whose behavior can be defined from the knowledge of its signals at discrete instants of time. - An asynchronous sequential circuit depends upon the input signals at any instant of time and the order in which the inputs change.

Synchronous sequential circuit

- employs signals that affect the storage elements at only discrete instants of time. - Synchronization is achieved by a timing device called a clock generator, which provides a clock signal having the form of a periodic train of clock pulses . - identified by clock or clk. - placed in such a way that storage elements are affected only with the arrival of each pulse.

Flip- flop

-It is a binary storage device capable of storing one bit of information. -In a stable state, the output of a flip-flop is either 0 or 1. -SR Flip-Flop -D Flip-Flop -JK Flip-Flop -T Flip-Flop

Gated SR Latch

-provides an Enable line which must be driven high before data can be latched. -When the Enable input is low, then the outputs from the AND gates must also be low, thus the Q and Q outputs remain latched to the previous data. Only when the enable input is high can the state of the latch change

Asynchronous sequential circuit

-storage element is commonly are time delay devices, whose storage capacity varies with the time it takes for the signal to propagate through the device. - a combinational circuit with feedback.

SR Latch

A circuit with two cross-coupled NOR gates or two cross-coupled NAND gates, and two inputs labeled S for set and R for reset. -in practical applications, setting both inputs to 1 is forbidden. -When using NAND gates, the outputs of the NAND gates stay at the logic-1 level as long as the enable signal remains at 0.

This circuit eliminates the undesirable condition of the indeterminate state in the SR latch to ensure that inputs S and R are never equal to 1 at the same time.

D Latch/ Transparent Latch

If the data on the D line changes state while the clock pulse is high, then the output, Q, follows the input, D. When the CLK input falls to logic 0, the last state of the D input is trapped and held in the latch.

D latch

Storage elements controlled by clock transition.

Flip-flops - edge sens

Storage elements that operate with signal levels.

Latches -basic circuit used for the construction of the flip-flop.

Master-slave D Flip-flop

Only the change in Master latch will bring change in Slave latch.

Flip-flop

a latch circuit with a "pulse detector" circuit connected to the enable (E) input, so that it is enabled only for a brief moment on either the rising or falling edge of a clock pulse.

The clocked sequential circuit uses these as storage elements.

flip-flops

Level Clocking

output can change during an entire half cycle of the clock.

Sequential Circuit is

specified by a time sequence of inputs, outputs, and internal states .

The state of a sequential circuit at a certain time depends on

the binary information stored in the storage elements at that time.