Ch. 2 Instruction Set Architecture

Pseudodirect addressing

where the jump address is the 26 bits of the instruction concatenated with the upper 4 bits of the PC and two trailing 0 bits. PC(31-28) - 26 bit instr address - 00 J-format instructions i.e. "j target"

Typical instruction classes

○ Instruction classes are collections of ISA instructions that have similar areas of functionality that can each represent high level language constructs. - Arithmetic: add, sub, addi - Data Transfer: lw, sw, lb, lbu, lhu, sb, lui - Logical: and, or, nor, andi, ori, sll, srl - Conditional Branch:beq, bne, slt, slti, sltiu - Jump: j, jr, jal

Addressing Types

register addressing immediate addressing base addressing pc-relative addressing pseudodirect addressing

Memory Operands

scalar data - one element of data composite data - arrays, structures, dynamic data (what main memory is for) MIPS 32 is byte addressable and big endian the address of a dataset is the lowest memory address involved

immediate addressing

the operand is a constant within the instruction itself § addi R1, R2, 4

Base Addressing

the operand is at the memory location whose address is the sum of a register and a constant in the instruction § lw R1, 8(R2) == load word into R1 at R2 + 8

PC-relative addressing

An addressing regime in which the address is the sum of the program counter (PC) and a constant in the instruction * 4. § Branching beq, bne Branch Target Address = PC + 4 * offset

Procedure Calling Operations

Call - definition - example J-Format instr jal - jump and link address of next instr in %ra - jal Label R-format instr jr - jump register copies $ra to program counter - jr $ra

Byte/Halfword Operation

Call - definition - example lb - load byte - lb rt, offset(rs) lbu - load byte unsigned - lbu .... sb - store byte - lh - load halfword - lhu - load halfword unsigned - sh - store halfword - lui - load upper immediate - lui $s0, 61 to load a 32-bit constant you can use a combination of lui and ori since immediate operands are always treated as a 16 bit value. lui will insert an immediate value into the upper 16 bits of the register annotated and ori will insert and immediate value into the lower 16 bits of the register annotated given the register has been inistialized to 0

Instruction formats - I-Type

I-Type: handles instructions with immediate operands Op-> Rs -> Rt -> Constant or address 6 -> 5 -> 5 -> 16 § addi R1, R2, 4 § lw R1, 8(R2)

ISA

Instruction Set Architecture: the specific set of low-level instructions available to a CPU. Differs for various CPU types (Intel Pentium, Mac G4, etc). Instructions and everything about them, MIPS is one. An abstract interface between the hardware and the lowest-level software that encompasses all the information necessary to write a machine language program that will run correctly.

Instruction formats - J-Type

J-type: handles instructions for jump functionality Op -> Address 6 -> 26 § j target jal target

Big endian and little endian

Little and big endian are two ways of storing multibyte data-types. In little endian machines, the last byte of binary representation if the multi-byte data type is stored first. In big endian machines, the first byte of binary representation of the multibyte datatype is stored first.

Constant Zero

MIPS register 0($zero) is the constant 0 makes possible nonexecutable instructions such as mov - mov R1, R2 == add R1, R2, $zero

Logical Operations

Operation - C - MIPS shift left - << - sll shift right - >> - srl bitwise AND - & - and, andi bitwise OR - | - or, ori bitwise NOT - ~ - nor

Instruction formats - R-Type

R-Type: handles instructions with register operands OpCode -> Rs -> Rt -> Rd -> Shamt -> Funct 6 -> 5 -> 5 -> 5 -> 5 -> 6 § add R1, R2, R3

instruction format types

R-type 6 5 5 5 5 6 I-type 6 5 5 16 J-type 6 26

Operand Types

Register - data is in a register Memory - data is in memory Immediate - data is part of the instruction

Operand types

Register Operands: data is in the register § add R1, R2, R3 Memory Operands: data is in memory § sw $t0, ($t1) Immediate Operands: data Is part of the instruction addi $t0, $t0, 4

Register addressing

Register addressing: the operand is a register § add R1, R2, R3 Immediate addressing: the operand is a constant within the instruction itself § addi R1, R2, 4 Base addressing: PC-Relative addressing: An addressing regime in which the address is the sum of the program counter (PC) and the constant in the instruction. § Branching beq, bne Pseudodirect addressing: the jump address is the 26 bits of the instruction concatenated with the upper bits of the PC J-format instructions i.e. "j target"

Sign extension and zero-extension

Sign extension and zero-extension are methods in which signed and unsigned numbers can be "extended" to fit in larger storage containers like a halfword signed int 4 being placed into a 32 bit register. Sign extension corresponds to signed numbers while zero-extension corresponds to unsigned numbers. Sign extension 4-bit -4 -> 8-bit -4: 1100 -> 1111 1100 Zero extension 4-bit 10 -> 8-bit 10: 1010 -> 0000 1010

range of an n-bit signed number

[-2^(n-1), 2^(n-1) - 1]

range of an n-bit unsigned number

[0 - 2^(n) - 1]

Conditional Operations

branch - definition - example beq - equal - beq rs, rt, L1 bne - not equal - bne rs, rt, L1 bgt - greater than - bge - greater than or equal to - blt - less than - ble - less than or equal to - j - unconditional jump - j L1 slt - set less than (signed) - slt rd, rs, rt : rd = rs < rt ? 1 : 0; slti - set less than immediate (signed) - slti rt, rs, constant sltu - set less than (unsigned) - sltui - set less than immediate (unsigned) -

Parameter passing

call-by-value - modify data in register call-by-reference - modify data in memory using address

how to convert to and from 2's complement

invert the bits and add 1