cpe 233 labfinal (lab questions)
Moore-type FSMs are often considered "slower" than Mealy-type FSMs. Briefly explain what the notion of "slow" refers to in this case and briefly explain why Moore-types FSMs are "slower"
"Slow" in this case refers to how fast the outputs can change in the circuit. Mealy-type FSM's output can change when external inputs change, opposed to Moore-type FSM's that have to wait for the next clock cycle to change outputs
List at least two reasons why lead zero blanking is a great idea to use, particularly in embedded systems.
1. Leading zeroes can cause problems if trying to use the data to do calculations, as numbers with leading zeros may require special handling. 2. saves power
The stack is a useful "mechanism" in MCUs and we refer to the stack as an "abstract data type". Define ADT in your own words and in the context of computer hardware.
An abstract data type is a data type whos behavior is defined, but not implementation. In the context of computer hardware, an ADT can be thought of as a way of organizing and managing data in a way that is independent of the specific hardware being used. Common stack uses in hardware, like push and pop, are abstracted away and we can utizilize it without needing to understand exactly how hardware is implementing it.
Brief explain why the state diagram listed in Figure 20 is only a "partial" state diagram. For this question, only consider the timing diagram associated with this experiment. This question has nothing to do with interrupts.
Figure 20 is a partial state diagram, because it is missing key outputs from the FSM. While the states are labeled, and the transitions are clearly defined. What each state does at a hardware level is not clear. This was done to avoid "giving away" the experiment, as well as to convey the approach without the details.
In assembly language-land, we refer to instructions that do nothing as "nops" (pronounced "know ops"). In academia, we refer to "nops" as administrators. The nop instruction in RISC-V MCU is pseudoinstruction. Show at least four different ways you can implement a nop instruction in RISC-V assembly language.
Four different ways you can implement a nop instruction in RISC-V assembly language are 1) mv x0, x1 2) addi x11, x11, 0 3) add x11, x11, x0 4) andi x11, x11, 0xFFF (12 bit limit)
I simplified my design such that the included FSM contains one less state than the previous design iteration. Briefly explain whether I reduced the memory requirements for the design or not
If you did not modify the width of the state (ps/ns) variables in hardware (verilog), you did not change the memory requirements for the design. In this exp, we can have up to 4 states with the given bit width of the variables without incrementing memory. Using less states does not mean we reduced memory requirements.
What is the official term for the item the stack pointer is pointing at in the RISC-V MCU Hardware?
In RISC-V MCU hardware, the item that the stack pointer is pointing at is commonly referred to as the "top of the stack".
For the RISC-V MCU, there is only one state associated with the interrupt cycle, which means that the FSM only requires one clock cycle to complete the interrupt cycle. Briefly but completely describe in general what dictates how many states (or clock cycles) a given MCU requires for the interrupt cycle. This question considers "states" and "clock cycles" as the same thing.
In general, for a given MCU, the amount of tasks that need to be done in order to support the interrupt architecture of a given MCU dictates how many clock cycles a given MCU needs for an interrupt state.
Briefly describe whether the "instruction memory" part of the MEMORY module is bit, byte, halfword, or word addressable. Fully explain your answer.
In instruction memory, part of MEMORY module, all the instructions must be 32 bits, therefore it is word addressable
Is it possible to have two of the same labels in an assembly language program? Briefly but completely explain. If this is possible, show an example in your explanation.
It would be possible to have two of the same labels in an assembly language program. If the program was just executing line for line top to bottom code execution, it would not be a problem. However, if you were using jumps to make loops and were trying to get into one of those labels, the program would not know which one to go to, which is why we never do it. EX: Init: li x20, x0 Loop: addi x20, x20, 1 Loop: addi x20, x20, 1 j Loop
Key difference between Mealy and Moore
Mealy - output based on state and external signals Moore - output based on state only
Briefly explain whether a Mealy-type output can act like a Moore-type or Mealy-type output.
Mealy output can act like a Moore-type by only depending on current state. Since Mealy can depend on current state and current output, you can adjust it to act like the Mealy-type output which only acts on the current state.
Briefly describe whether the FSM used in the RISC-V OTTER MCU is a Mealy or a Moore-type FSM.
Mealy, the FSM in the RISC-V OTTER depends on an input OPCODE.
Briefly explain whether a Moore-type output can act like a Moore-type or Mealy-type output.
Moore-type can only act like a Moore-type output due to it only being able to depend on current state. It does not have the functionality to depend on current output.
Could you use the addi instruction to add an immediate value of 0x7421 to another register? Briefly explain why or why not.
No, the assembler encodes the immediate value for the addi instruction as a 12-bit signed value, which has a range of [-2048,2047]. 0x7421 is outside this range
Briefly explain why stack overflow and underflow are major issues in assembly language programs.
Overflow and underflow are cases in which the stack grows beyond the bounds designated for the stack in memory (these bounds are from 0x0000_F000 to 0x0000_FFFF). These are typically caused by mismatched push/pop instructions or by incorrectly jumping to a subroutine. Stack overflow/underflow can be a major problem for your program because it will lead to overwriting data, and consequently losing that data - when a later instruction calls for the retrieval of that data, it will instead get whatever is in the stack.
Briefly describe the difference between port mapped I/O and memory mapped I/O.
Port mapped I/O and memory mapped I/O are two approaches for interacting with external devices in a computer system. In port mapped I/O, a separate address space is dedicated to I/O operations, where devices are accessed using specific port numbers or IDs through dedicated IN and OUT instructions. On the other hand, in memory mapped I/O, devices are treated as memory locations within the same address space as the system's memory. Devices are accessed through normal memory read and write operations, without the need for dedicated I/O instructions.
The default action for interrupts in the RISC-V Otter MCU is that they are masked upon entry to the ISR, and later unmasked upon exiting the ISR; this means that without intervention, the interrupts returned unmasked. Briefly describe the procedure of how programmers return from interrupts with the interrupts disabled.
Programmers return from interrupts with the interrupts disabled my saving the return address of whatever instruction they last left off on
List the six RISC-V OTTER MCU instruction formats.
R- Format, I - Format, S - Format, B - Format, U - Format, J - Format
I just added 34 new instructions to the RISC-V instruction set to support the application I'm working on. Is the RISC-V MCU still a RISC-V architecture or not? Briefly but fully explain.
RISC-V stands for "Reduced Instruction Set Computer" and to be a RISC architecture does not matter on how many instructions are added but on the complexity of the instruction as compared to the other architecture type of CISC. If all the instructions are simple and reduced, then it should still be an RISC architecture type.
We often consider the ISR code as having a "higher priority" than the non-interrupt code. Briefly but fully explain this concept.
The ISR code has "higher priority" because it has the ability to switch from the normal program flow into an interrupt state where it executes the ISR codes. When the ISR is being executed the interrupts are disabled, so the program may be missing some important event while processing the interrupt. The longer the ISR takes to complete, the longer the main program is delayed. The shorter we keep our ISR code, the less we will miss out on.
State whether the RISC-V MCU is a RISC or CISC processor. Support your statement with at least three characteristics regarding those two types of computer architectures.
The RISC-V MCU is a RISC processor. 1. Compared to a CISC processor with complex instructions, the RISC-V has simple instructions. 2. CISC processors may have many instructions that execute in a different number of clock cycles. The RISC-V MCU instructions execute in the same number of clock cycles (besides load-type instructions) 3. RISC-V has a larger register file compared to CISC
Briefly describe whether the RISC-V OTTER wrapper registers the input data (as in input/output) or not.
The RISC-V Otter wrapper does not register the input data, it receives the port addresses from the inputs on the switches on the board and these addresses go into the RISC-V MCU, which handles all of the input data.
Briefly explain why the PC advanced by 4 when it is executing instructions.
The RISC-V instruction set architecture is 32 bits wide. Each instruction in memory is 4 bits after each instruction. The PC advances by 4 when it is executing instructions, and when it finishes an instruction, it will continue to the next instruction by advancing 4 bits.
Briefly explain why the data output from the MEMORY module associated with the jal, jalr, and branch inputs produced junk on the outputs (unknown outputs) for this experiment (2).
The data output from the MEMORY module associated with jal, jalr, and branch produced junk on the outputs for this experiment because the relative addresses associated with the instructions don't have any data in the memory. The only instructions stored in the module are 4, 8, 12, etc.
Briefly describe what (or who) determines the number of instruction formats a given instruction set contains. No, the answer is not the ISA
The designers determine the number of instruction formats a given instruction set contains. There are many things that designers take into account when determining the number of instruction formats, such as efficiency, functionality, time, and readability.
We use the stack for "general data storage", but we typically use the stack to store information in two scenarios. What are those scenarios and what information does the stack store?
The first scenario we use the stack to store information is if a subroutine needs access to registers that are already used. In order to keep the previous values from the registers that were changed, we store the values in the stack after the subroutine is finished. Here, we are storing and restoring context. The second scenario we use the stack to store information is for return addresses.
Briefly define the general purpose of assembler directives.
The general purpose of assembler directives is to give the programmer some measure of control over the operation of the assembler. Thus the assembler directives are messages from the programmer to the assembler.
Briefly explain why the two LSBs of the PC's output are not connected to the memory module.
The instruction memory always advances by 4
Why does there need to be different inputs associated with the jal and jalr instructions? Examine the instruction's explanations in assembly language manual for this question.
The jal and jalr instructions have different inputs. Jal uses an rd and an imm value, while jalr uses rd, rs1, and imm. The jal instruction calls for a destination register with a specific address (a fixed value). The jalr instruction is used for indirect jumps through a target register and a return address register.
You can use either the jal or jalr instruction to call subroutines, but you can only use the jalr instruction to return from subroutines. Briefly explain why this is the case.
The jalr instruction is an I-type instruction and has a 12-bit immediate field to code a relative address to jump while the jal instruction is a J-type and has a 20-bit immediate field to encode the relative instruction. When you return from a subroutine, it is required that the MCU load the return address into the PC which is stored in a register when the branch subroutine is issued. Since the jal does not include a register in the jump address calculation, it cannot return from subroutines.
Program control instructions rely on labels in the code to be encoded and subsequently work properly. If you look at the machine code for a given program, it contains no labels. Briefly explain how the machine code gets away with not encoding labels.
The machine code can get away with not encoding any labels because when the machine code is processed it will represent the memory address of the data value. We use labels to refer to the location of the data values of instruction so if we did add labels to machine code it would be redundant.
What is the significance of this value: -559038737. HINT: change the radix to hex. Describe an instance there using this value would be helpful to humans debugging your hardware.
The significance of -559038737 is a signed int that when converted to binary and then converted to binary to hex translates to DEADBEEF and this is a significant magic debug value that is used to mark newly allocated areas of memory that had not yet been initialized.
The problem described in the previous problem can be avoided, thus making it possible to disable interrupts under program control without compromising the overall operation of the MCU. Describe how the situation can be avoided when the MCU acts on an interrupt.
The situation can be avoided by keeping the width of the interrupt pulse short
As you know, part of the interrupt architecture includes the RISC-V MCU automatically masking the interrupts. This being the case, why then is there a need to keep the overall output pulse length of the interrupt relatively short?
There is a need to keep the overall output pulse length of the interrupt relatively short because if it is too long, the same interrupt can be processed twice.
Can you write a RISC-V MCU assembly language program that "stops running"? Briefly explain your answer.
There is no way that you could implement in the RISC-V MCU assembly language program that "stops running" and will stop the program from executing instructions under the program. The closest thing that would stop the instruction from being called would be to implement an endless loop.
Briefly but completely explain why, in general, keeping your ISRs are short as possible is the best approach
This is the best approach because it decreases response time and avoids blocking other interrupts. The response time is significant because the ISR handles conditions like interrupts that require immediate attention, so keeping the ISR short makes the system respond faster, minimizing delays. This also means a faster processor
Nested subroutines are quite common in assembly language programming. Accordingly, there is also the notion of nested interrupts. The RISC-V OTTER does not support nested interrupts, but if you wanted to break your program by allowing interrupts to nest, how would you do that under program control on the RISC-V MCU?
Under program control, you would need to save and restore the address of the current interrupt you are processing so that you can come back to it if the MCU acts on another interrupt before it finishes.
Briefly describe how you could "add some hardware" to the RISC-V Otter MCU that ensure disabling interrupts under program control will be a viable solution.
Use a one shot module to make the interrupt signal the perfect length(Not too short or not too long).
Describe a situation where a NOP instruction or a NOP-type instruction would be useful.
When you need to implement a delay
Despite not mentioning the topics much in this course, setup and hold times are important in digital design. Your experiment worked, so briefly describe how this experiment handled meeting setup and hold time issues.
Wrapper has a clock divider, it allows data to travel before the next clock cycle
Is it possible to have two or more labels in an assembly language program with the same numerical value? Briefly but completely explain. If this is possible, show an example in your explanation.
Yes it is possible. junk: junk1: add x1, x3, x3 junk and junk1 have the same relative address because the pc just focuses on where the next instruction is. In this ex, both labels are associated with the add instruction.
The RISC-V MCU has 32 "general purpose" registers. Briefly describe why RISC-V MCU programmers should never use registers x1 and x2.
x1 is used as the return address when calling subroutines x2 is used as the stack pointer which points to the top of the stack.
What is the maximum number of different unique bits that you could configure the RISC-V MCU to input? Briefly but fully explain. Write an equation; don't generate the final number.
(2^32 - 2^16) * 32 2^32 is total address space, 2^16 is reserved for physical memory (so subtract)
What is the maximum number of different unique bits that you could configure the RISC-V MCU to output? Briefly but fully explain. Write an equation; don't generate the final number.
(2^32 - 2^16) * 32 2^32 is total address space, 2^16 is reserved for physical memory (so subtract)
What is the capacity of the MEMORY module? List the capacity in both bytes and words. Examine the source code for the MEMORY module to answer this question.
16k Words (1 word is 32 Bits) 64k Bytes
How much memory do the control units in this experiment contain?
2 bits, allows for 4 states (F, E, WB, and interrupt state). DCDR is combinatorial and has no memory
Based on your circuit design in this experiment(1), can you determine how many clock cycles after the button press your design requires to complete the assigned task? If so, how many clock cycles does your design require to generate the requested result? If not, explain why it is not possible to calculate the number of clock cycles.
After the button press, our circuit needs 32 clock cycles to complete the assigned task. It takes 16cycles / counts to go through each address of the two ROMs, keep track of how many valid values there are, and write into the associated address of the RAM. It then takes another 16cycles / counts to display all the contents within the RAM at each address.
Briefly but completely describe the major problem with the RISC-V MCU receiving an interrupt while the MCU is in the act of processing an interrupt. For this problem, consider the interrupts masked when the MCU receives the interrupt.
Assuming interrupts are masked when received, the key problem here is missing an interrupt. This problem is mitigated by saving (holding) the interrupt, and keeping it asserted until the MCU confirms that it has been received.
Briefly explain why you should implement the PC as a simple register instead of a counter as the name implies
Counters can load values like a register, but counters typically increment by 1 for the output sequence, which is not what we want. we need our pc to be able to jump to different addresses and increment by 4 (instruction memory advances by 4)
The PC has two types of input signals: control signals and data signals, where we consider the clock input a type of control signal. List which inputs are data inputs, and which are control inputs.
Data Inputs: jalr, branch, jal (actual data being loaded into PC) Control Inputs: rst, PCWrite, pcSource, clk (control if, when, and what type of data being loaded)
In your own words, provide a simple definition for digital design.
Digital design is the process where you create a digital circuit to solve a given problem. In modern digital design, the goal is to keep circuits as simple as possible, in order to improve efficiency. In digital design, problems are solved by having outputs react to inputs in a circuit
Briefly describe how the MCU differentiates between load/store and Input/Output instructions. For this problem, we're not talking about the opcodes associated with those instructions.
For the load instruction, the MCU reads from memory and writes data into a register from memory, and for the store instruction, the MCU copies data from a register and writes the data from the register into memory. However, for input/output instructions, the RISC-V uses "memory mapped" I/O, where it does not need the normal memory instructions when dealing with I/O; instead, there are certain memory addresses accessed when dealing with external hardware. The main difference between the load/store and Input/Output instructions is that the load/store instructions access memory and the I/O instructions access data from the outside world.
If you were not able to use a LUT for this experiment, briefly but completely describe the program you would need to write in order to translate a given BCD number into its 7-segment display equivalent.
Going from BCD to binary (for each digit) would be done the same way as with a LUT. You need to convert a binary number to its visual representation on the 7 seg. You can write a case/switch statement, where the binary number is checked in a series of big statements, and output values are set according to the case.
There are five instruction types that include immediate value; list which of those types are signextended by the IMMED_GEN module.
I, S, B, and J types are the instruction types that are sign extended by the IMMED_GEN module.
How does IOBUS_WR affect wrapper?
IOBUS_WR lets us know if MCU performed input/output operation that should be displayed. Input/Output when address > FFFF, data/instructions when address < FFFF
Briefly describe what a t-cycle is in the context of an FSM.
In the context of an FSM, a T cycle refers to a single unit of time used to synchronize the operations of the FSM and ensure that the states and operations are both updating synchronously.
We generally consider interrupts "asynchronous" in nature. However, the RISC-V MCU processes everything synchronously. Briefly describe what it means for the interrupts to be asynchronous and how exactly the MCU processes them in a synchronous manner.
Interrupts are considered to be "asynchronous" because interrupts can happen at any time, and there is no exact time for them to happen, so we really do not know when we can get an interrupt. The interrupt also is not part of the normal program flow, and requires the MCU to stop executing the normal program flow in order to pay attention to the interrupt that occurred. The MCU processes interrupts in a synchronous manner. When it gets an interrupt, it will first complete the current instruction it is on, and save the address of the next instruction to come back to. The ISR address is saved and the MCU will jump to it once the MCU is done processing the current instruction. Once the MCU finishes processing the interrupt, it restores the saved address of the next instruction to jump to once the ISR is finished, and resumes normal program flow starting at the saved return address.
Interrupt architectures generally always automatically mask interrupts upon receiving an interrupt. Briefly but completely describe why this is a good approach, and a better approach than attempting to rely on masking the interrupts under program control.
It is a good approach because it allows the MCU time to do the processing required in the ISR without risking acting on another interrupt signal. Another reason is because we have the mret instruction return the MIE bit to the state it was previously in when the MCU received the interrupt. If the programmer needed to return the interrupt unmasked they'd have to clear the MPIE bit in CSR[mstatus] before returning from the ISR. This is a better approach than relying on masking interrupts under program control because it is risky and requires the programmer to manually manage the interrupt enable and disable states.
Briefly but completely explain why it is "really hard" to see the outputs of the universal seven-segment display module on the simulator's timing diagram output even though the module has a valid data input.
It is hard to see the outputs of the universal seven-segment display module on the simulator's timing diagram output even though the module has a valid data input because the universal seven-segment module uses the system clock, but also utilizes internal clock dividers, so it's complicated to use the modules outputs to verify if a circuit has properly simulated on the timing diagram. Also, it is hard to see the outputs of the display module because of the block nature of the modules, and the multiple binary values representing the display segments.
Word on the street is that polling is bad because it makes your programs operate "less good". My RISC-V application uses a few different polling constructs; does this make me a bad programmer? Briefly but completely explain.
Just because you use a polling loop in your construct, it does not necessarily make you a bad programmer. If the MCU is not processing anything that is meaningful, then the use of polling is completely okay and does not hurt the program at all. If response time is not a big deal in the current place of the program and there are no background computations, then polling does not hurt the program either. So, you are not a bad programmer.
Briefly but completely describe why the load-type instructions (lb, lbu, lh, lhu, and lw) require three cycles to execute.
Load-type instructions require three cycles to execute due to the writeback state. In a load-type instructions execute state, it generates a memory address. The memory address is used in the writeback state to read data from main memory and write it to the register file.
f the PC were to advance every clock cycle, could the RISC-V Otter memory output ever show the data associated with the current value on the PC's output? In other words, could the output of the memory ever be associated with the current output of the PC. Briefly but fully explain your answer in terms of the operating characteristics of the MEMORY module.
No, because memory has synchronous reads. Instead of the data associated with the current value being shown, it would be the data associated with the previous value of the PC's output. It takes an extra clock cycle after the read for the data in memory to be outputted.
Briefly explain whether the use of enumerated types in SystemVerilog increases the size of the synthesized design.
No, the use of enumerated types in SystemVerilog does not increase the size of the synthesized design. Enumerated types in SystemVerilog are just a set of named values that are given possible values. Since enumerated types are just a shorthand for a set of integer constants, they do not add any extra logic or complexity to the design. The synthesizer simply just maps the enumerated values to their corresponding integer values.
Why is it that we need to match call/return instruction pairs (meaning the order they are called in matters) but we don't need to follow a similar approach with push/pop pairs. Briefly but fully explain.
Pushing and popping do not matter because in RISC-V, the instruction set does not have designated push/pop instructions. For call instructions, it saves the return address on the stack, and the return instruction retrieves the return address from the stack and transfers control to that address. If the call/return pairs are not matched properly, the return instruction may retrieve the wrong return address from the stack.
Briefly explain why this experiment asked you to include the dump file associated with the assembly language program in the lab submission.
So you can compare to timing diagram
Sometimes the "li" pseudoinstruction causes the assembler to generate two instructions and sometimes one instruction. Briefly describe why this is the case and list the two different instructions
The "li" instruction will generate one instruction if the immediate value fits within 12 -bits, if it does not fit within 16 bits, the assembler will generate two instructions. The single instruction that is made when the immediate value is less than or greater to 12 is the addi instruction, with the destination register as the same as the source register, and the immediate values as the second operand. In the case where the immediate value does not fit in between 12 bits, the first instruction loads the upper 12 bits of the immediate value to the destination register. Then the second instruction loads the lower 16 bits of the immediate value into the destination register. (lui + addi)
Briefly explain what attribute of the RISC-V MCU is preventing you from executing all 2-cycle instructions in one clock cycle.
The 'fetch' cycle (getting data from memory) is synchronous so it needs an entire clock cycle.
Briefly describe why the IOBUS_ADDR is an output from the ALU and not from a register or directly from memory.
The ALU is responsible for performing the calculations/data manipulations required for the I/O operations. The IOBUS_ADDR is a signal that is used to specify the memory address or device address for the I/O operations. The IOBUS_ADDR is an output from the ALU because the ALU calculates and manipulates the data then sends the address to the IOBUS_ADDR so it can initiate the correct I/O operation.
I have this strong desire to implement an instruction such as "add x3,x4,x5,x6", where the three right-most operands are summed and the result is stored in the left-most operand. Briefly but completely describe the changes in hardware (to existing RISC-V Otter modules only) that I would need to implement such an instruction.
The ALU would need to take in more inputs because the add function wants to take in two more arguments. ( need something else ) , as well as the decoder, register, and control unit
Briefly describe how the AND gate in the RISC-V MCU schematic helps control the ability of the MCU to process interrupts.
The AND gate acts as a switch that either blocks the INTR signal or allows the INTR signal to pass through to the CU_FSM. When the AND gate is outputting a zero, the CU_FSM will not receive an interrupt, meaning the interrupt is being "masked" or disabled. When the signal is high, the interrupt is being "unmasked" or enabled. The AND gate helps control the ability of the MCU to process interrupts by letting it focus on other tasks rather than dividing its attention to always be waiting for interrupts.
Describe whether you implemented your circuit using a Mealy or Moore-type FSM. Briefly state the reasons why you choose one FSM model over the other. (exp 1)
The FSM model that we decided to implement our circuit with was a Mealy-Type FSM. The reason for this is because in order for our circuit to start, it was required to have a button that would set the circuit into motion. A mealy-type FSM has output values that are both determined by its current state and the current inputs. The current input in this case would be the "BTN" signal. You would choose one FSM model over the other if you didn't require both input and output state and in doing so, you can minimize the amount of states you would need, making your circuit more efficient.
The design of the RISC-V MCU ISA intentionally shares as many fields as possible in the six different instruction formats. Briefly explain the reason why the ISA designers did this.
The RISC-V-MCU ISA shares as many fields as possible in the six different instruction formats, and this reduces the hardware complexity, and reduced complexity leads to shorter run time and more efficient code.
List the accepted basic parts of a computer.
The accepted basic parts of a computer are the processor, memory, and input/output devices.
Briefly explain the advantage of making an FSM, such as the one you used in this experiment, independent of external factors such as how much data the design will process.
The advantage of making an FSM that is independent of external factors makes it more reusable.
My homework assignment is to implement 25 new pseudoinstructions. Briefly describe what "entity" I'll be using to complete this assignment.
The assembler is the entity that will be used to complete the assignment. The assembler takes in the instructions and processes them through its modules.
Briefly but completely describe the major problem with the RISC-V MCU receiving an interrupt while the MCU is in the act of processing an interrupt. For this problem, consider the interrupts unmasked when the MCU receives the interrupt.
The major problem with receiving an unmasked interrupt while the MCU is processing one is that the MCU will have to act on it. The MCU only acts on unmasked interrupt signals so it will stop processing the current one and skip to the next one. This can cause data to be misplaced in registers or a certain program in the ISR to not function properly.
If the "memory" portion of RISC-V MCU memory changed from 2^16 x 8 to 2^10 x 8, what would be the new maximum number of unique input and/or output addresses that the hardware could use? Answer this problem with an equation. Read the problem very carefully.
The new maximum number of unique input or output bits that could be addressed would be: 32 * (2^32 - 2^10)
Briefly describe who or what decides on the number of t-cycles a given computer architecture uses
The number of t-cycles a given computer architecture uses is determined by different factors of the computer, such as clock speed, complexity of the system, and desired performance. The designers behind the computer are in charge of these elements, and ultimately have control over the design of their computer and these factors.
If the RISC-V Otter MCU hardware did not automatically mask the interrupt, there could be a big problem if the MCU could only mask the interrupts under program control. For this question, briefly but completely describe the problem.
The problem of only being able to mask interrupts under program control is that you could receive another interrupt signal while the MCU is still processing the previous interrupt and hasn't masked it yet. The problem is missing an interrupt signal in the midst of processing one and not being able to quickly prepare for the next signal
In your own words, describe the relationship between the programming model and the instruction set of a given computer.
The programmer's model set shows you which hardware the programmer has control over; you control that hardware with the instructions in the instruction set
Which signal(s) in the control units represent the memory elements for the control unit.
The signal in the control unit that represents the memory elements is the present state. How much memory is there (must look at code for ps) 2bits. How wide is the present state? (Declared in code)
Briefly describe whether the MEMORY module in general is bit, byte, halfword, or word addressable. Fully explain your answer.
The smallest chunk of data you can get out of memory is a byte. Therefore it is byte addressable.
There is obviously no "stack" module in the RISC-V MCU architecture diagram. Where exactly is the stack then on the RISC-V MCU?
The stack is a designated area in our memory.
Briefly describe at least two limitations of the RISC-V MCU ALU.
The two limitations of the RISC-V MCU ALU is that it is only 8 bits and that the ALU does not have a multiply or divide operation for any other number besides 2.
Briefly but completely state and explain in your own words the two main aspects of the modern digital design paradigm.
The two main aspects of the modern digital design paradigm are that digital logic circuits are hierarchical, and modular(digital logic circuits are decomposable into a few basic digital circuits). The first main aspect, digital circuits being hierarchical, means that there are many levels at which we can describe a digital circuit in order to provide us with as much information as possible. The second main aspect, modular digital circuits being decomposable into a few basic digital circuits, means that we typically build digital circuits out of many simpler digital circuits, and connect them together.
Did the universal seven-segment display device used in this experiment employ lead zero blanking or not? Briefly but completely answer this question in such a way as I know that you know what lead zero blanking is.
The universal seven-segment display device used in this experiment employed lead zero blanking because when displaying a single digit number, there was no zero that showed up in the tenth place, instead, the tenth place was blank when displaying single digit numbers.
How much memory does the RISC V Wrapper have
There are 3 registers in the wrapper, one for LEDs(16 bits), one for SEGS(8 bits), and one for AN(4 bits), so 28 bits in total.
Being that there are two add-type instructions (addi & add), briefly explain why there is only one "add" operation associated with the ALU.
There is only one "add" operation because this "add" operation is used to add two values in two different registers and store them in a register. The "addi" instruction is used to add an immediate value to a value in a register. Since there is only one "add" operation, this simplifies designs and documentation, which makes things a lot easier to understand for the programmer.
You wrote assembly code for this experiment. Briefly but completely explain whether this code was software, firmware, or Tuppaware.
This code was firmware. It is utilized by the hardware, using specific instructions that the RISC-V MCU supports. Other MCU's may not be able to understand the assembly code we wrote, as they may not support the same instructions (ex a CISC MCU), making the code firmware. Software on the otherhand can be understood and run on anything, no matter the hardware.
Assembly languages are not considered "portable". Briefly describe what this means and why this is the case.
We refer to computer languages as being portable because a portable computer language means that you can write this language for any architecture without actually knowing anything about assembly language. Assembly instruction sets are specific to certain hardware, so they are not portable.
Briefly explain whether the RISC-V Otter handle operations on both signed and unsigned data
Yes, the RISC-V Otter can handle operations on both signed and unsigned data. The RISC-V Otter has different versions of instructions for signed and unsigned numbers.
Can I possibly use the RISC-V to implement a program that utilizes 40 stacks? If so, briefly but completely explain how this can be done using the ISA and not changing hardware. Assume the amount of memory is not an issue for this problem.
Yes, we can use the RISC-V to implement a program that utilizes 40 stacks. This can be done by using the ISA to reserve a block of memory that can hold 40 stacks. Then we can allocate a register to keep track of the current sp. After this, we can use the "call" instruction to choose which stack we want.
Can you use the same I/O port address for both inputs and outputs in the same complete RISC-V MCU implementation? Briefly explain.
You can use the same I/O port address for both inputs and outputs in the same complete RISC-V MCU because the same addresses are being used by different hardware, since the input and output will have different hardware. For example, the RISC-V MCU can have a mux for input, and a register for the output, two different pieces of hardware that can share the same address. The addresses can be configured to be used as either an input or an output depending on the situation.
Here is a quote from this experiment(8): "If you write your program in such a way that your program requires a stack"... So you often have a choice of when you use a stack or not. Briefly explain what determines whether your program requires a stack or not.
Your program will require a stack if you need to save and restore context in a subroutine (changing registers that are not expected to change when going back to the code that called that subroutine), or if you need to save a certain return address for nested subroutine calls
In computerland, we typically increase the bit-width of data in two ways. List those two ways and describe what type of data they are used on.
there are two methods to increase the bit-width of data: sign extension and zero extension. Sign extension is typically applied to signed integer data, whereas zero extension is commonly used for unsigned integer data.
