CS132 - Computer Organisation and Architecture
Describe the layout of a PLA
An array of AND gates, with an input for each PLA input and it's negation. The output feeds into an identical array of OR gates. Breakable fuses at each AND/OR gate allow inputs to be configured.
What is an N-bit counter?
An array of D-type latches, where each latch's input is the negation of their output (¬Q). The clock is directly connected to the first, but is given as the output of the previous latch for each subsequent latch.
Describe a three-state bus
An array of three-state buffers place their output onto a common line. Only one buffer should be enabled at any one point.
Describe the use of a "parity" bit
An extra bit is sent with messages to verify no errors have been encountered (due to noise)
What does ALU stand for?
Arithmetic Logic Unit
How can individual memory chips be combined?
Arranged in a grid
Why are binary signals used in computing?
Binary provides noise immunity
How can a truth table be created from a logic circuit more easily?
By listing intermediate values
How can propagation delay be reduced? (physical change)
By placing components closer together
What are the three sizes of register?
Byte (8 bits) Word (16 bits) Long (32 bits)
Describe fixed point representation for non-integer numbers
Columns are added to denote the fractional parts of a value (e.g. column for 2⁻¹, 2⁻² etc.)
What is the difference between combinatorial and sequential logic?
Combinatorial: output is a function of the present value of inputs Sequential: output is dependent on previous inputs (dependent on stored values)
What is another name for the status register?
Condition code register
Describe the fetch-decode-execute cycle
Fetch: - Instruction retrieved from memory location held by PC and stored in IR - PC incremented to next instruction Decode: - Retrieved instruction decoded Execute: - CU signals functional CPU components - May result in changes to data registers, PC, ALU, I/O etc.
State a potential problem with using parity bits
If an even number of "error bits" occur close enough together, the error will not be caught by the parity bit
Describe a checksum value
Like parity bits, but for each column when the sent messages are arranged on top of each other
What is the difference between macro and micro instructions?
Macro = an instruction defined simply but may take more than one CPU cycle Micro = an operation which takes one CPU cycle to complete
What does PC stand for?
Program Counter
Describe the method for conversion from decimal to binary
Repeatedly divide the number by 2, noting the remainder. Read the remainders backwards for the binary counterpart
State the truth table for an active-low flip-flop
S R | Q P 0 0 | X X 0 1 | 1 0 1 0 | 0 1 1 1 | no change...
What happens on the rising edge of the clock in an N-bit shift register?
The bit stored in each D-type latch is passed to the next. The first latch stores the value passed as the register's input. The last latch gives the previous value as the register's output.
How can a 2s complement number be formed using logic gates?
The bits are inverted using an XOR gate. 1 is added using the carry in
What happens on the rising edge of the clock in an N-bit register?
The bits given as the input bits are stored in the register
How are constants referred to in assembly?
# (e.g. #5)
State the range of an n-bit two's complement number
(-2ⁿ⁻¹) → (2ⁿ⁻¹-1)
What symbol denotes OR in a boolean expression?
+
How many bits can one octal symbol represent?
3
What is the status register used for?
Storing bits related to certain conditions arising in the ALU
How does a T-type latch differ from a D-type latch? What does T stand for?
T = toggle When enable and T are active, the value of Q is toggled: Q = ¬Q
What is the combined operation of the CU and the ALU called?
The CPU
Explain the concept of polled I/O
The CPU periodically checks for a change in status of a I/O device. It initiates processing on a change of status and handles transmission
Explain the concept of interrupts
The I/O device tells the CPU through an input on the CPU when it is ready. When it is ready, the working registers of the CPU are saved, the interrupt is serviced, then the registers are restored
What symbol denotes AND in a boolean expression?
.
Which takes precedence, . or +?
. takes precedence over +
How are the bits separated and used in a single precision IEEE floating point number?
1 bit for sign 8 bits for exponent 23 bits for mantissa
How many bits can one hex symbol represent?
4
How many bits in a nibble?
4
How many bits in a byte?
8
Why is a small cache enough to produce improved performance?
90% of memory accesses only within 2Kb
What is the format of an assembly statement?
<LABEL>: <OPCODE> <OPERAND(S)> | COMMENT
State the distributive law of boolean algebra (for + over . and . over +)
A + BC = (A + B)(A + C) A(B + C) = AB + AC
What do A and B denote in an AxB memory integrated circuit?
A = no. of words B = word length A rows and B columns
What is the truth table for a 1-bit half adder?
A B Sum Carry 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
What is a N-bit full adder?
A combination of 1-bit half adders, where the carry output from one is the carry input to the next
What is a decoder?
A component which activates one output pin for each possible combination of activated input pins
What is a multiplexer?
A component which allows a single input out of many to be passed as the single output, through "selection" inputs
What is a de-multiplexer?
A component which allows a single input to be passed to one of the many outputs, through "selection" inputs
What is a 1-bit full adder?
A component which performs addition of 3 bits: A, B and a previous carry 2 outputs: the sum, and an output carry bit
What is an encoder?
A component which takes multiple input pins (only one active at a time) and converts them to less output pins
Define the "carry" in an addition
A digit that is transferred from one column of digits to another column of more significant digits
What is a three-state buffer?
A gate whose output can be placed in a third state - UNCONNECTED. The gate has an "enable" line
Define "sequential logic"
A logic circuit whose outputs are logical functions of its inputs and its current state/memory
What is an N-bit register? What components form it, and what inputs/outputs does it have?
A multi-bit memory component, consisting of N D-type latches. Inputs = 1 input for each bit of the number to be stored, 1 input for clock. N outputs: 1 for each stored bit
Explain the concept of DMA
A new component - the DMAC is used to manage data transmission. 1. I/O device requests DMA transfer 2. DMAC passes request to CPU 3. CPU initialises the DMAC: - Input or output? - Start address - No. of words to transfer 4. DMAC requests use of buses 5. CPU responds when ready to surrender buses
How can a 1-bit half adder be represented using logic gates?
AND gate for carry XOR gate for sum
Describe the difference between active high and active low
Active high: 0 = inactive, 1 = active Active low: 0 = active, 1 = inactive
What is the job of the MDR?
Contains data fetched from memory or data ready to be written to memory
What is the job of the MAR?
Contains the address of the region of memory to be read or written (i.e. location of data to be accessed)
What is the job of the IR?
Contains the most recent instruction fetched
What does CU stand for?
Control Unit
State the disadvantages of interrupts
Data transmission is still controlled by the CPU Hardware and software is more complicated
What is the job of the CU?
Decodes program instructions and handles logistics for the execution of decoded instructions
What does D stand for in D-type latch? And why?
Delay When enable is active on the rising edge of a clock, the value of Q is only changed on the clock.
What does DMA stand for?
Direct Memory Access
How can address decoding space be minimised?
Divide address inputs into 2 parts - row addresses and column addresses. Column addresses uses a multiplexer (on output)
What is the motivation for the memory hierarchy?
Economics - fast memory is not cheap for large capacity. Large capacity memory is not fast. Both are required, so use both together (and everything in between)
What does ECC stand for and what does it mean?
Error Correcting Code Calculating both character and bit-column parity
What is a D-type latch? Name the inputs, outputs and values they take on different inputs
Essentially a 1-bit memory circuit 2 inputs, data (D) and enable 2 outputs, Q and ¬Q When enable is inactive, Q and ¬Q are unchanged When enable is active, Q takes the value of D, and ¬Q takes the value of ¬D
Describe the two types of parity system
Even parity system: The value of the extra bit is chosen to make total no. of logical 1s even Odd parity system: The value of the extra bit is chosen to make total no. of logical 1s odd
What is a cache?
Fast memory that can store a small amount of data
State the advantages of interrupts
Fast response No wasted CPU time (like in polling)
What are clocked flip-flops?
Flip-flops whose output changes only on the rising edge of the clock input
Describe the difference between active high and active low decoders
For each unique configuration... Active high: Single output pin is 1, rest 0 Active low: Single output pin is 0, rest 1
What is the standard for floating point representation? And what levels of binary precision does it specify?
IEEE Standard 754 Single precision (32 bits) Double precision (64 bits) Quad precision (128 bits)
Why is less total I/O pins in a memory chip not always desired?
It results in a long, narrow cell array
State the definitions of temporal and spatial locality
In a particular memory location is referenced: - It is likely that the same location will be referenced again soon (temporal) - It is likely that a nearby location will be referenced soon (spatial)
Describe the sections of the memory hierarchy
In order of fast → slow, expensive → cheap, small → large: R- Registers (on the CPU) R- Cache memory R- Main store S- Magnetic disk S- Tape/optical disk R=random access S=sequential access
What does IR stand for?
Instruction Register
What does MS stand for?
Main Store
What does MAR stand for?
Memory Address Register
What does MDR stand for?
Memory Data Register
What does MSB and LSB stand for?
Most Significant Bit Least Significant Bit
Describe two's complement representation
Most significant bit is negative
How is floating point representation similar to scientific notation?
Numbers are both expressed as mantissa × 10^(exponent)
Explain the concept of context switching
On an interrupt, the CPU completes its current instruction, then pushes the PC and the status register(s) onto the stack. The new PC is retrieved from the interrupt. When the interrupt has been serviced, the CPU pops the PC and the status register(s) off the stack and resumes its previous process
What must you remember when adding two two's complement numbers together?
Overflow should be ignored
What is the job of the ALU?
Performs mathematical/logical operations
State the disadvantages of memory mapped I/O
Portions of memory address space must be reserved
What are the 3 lines connected to a basic memory cell?
Select - enables the cell R/W - indicate read or write Data - input when writing or output when reading
What is the difference between an N-bit register and an N-bit shift register?
Shift register has one main input. The output of one D-type latch becomes the input of the next.
What is different about the representation of zero in signed magnitude representation and two's complement?
Signed magnitude has 2 values for zero (+0 and -0) Two's complement has a unique representation of zero
State the advantages of polled I/O
Simple software and hardware required
State the advantages of memory mapped I/O
Simpler than many alternatives Less internal logic required by the CPU Use of general purpose memory instructions
Describe signed magnitude representation
The left-most bit represents whether the number is negative 1 = negative 0 = positive
Define a "word"
The number of bits a machine can process simultaneously
What happens if parity error is detected?
The receiver will ask for retransmission
Describe memory mapped I/O
The same address bus is used to address both memory and I/O devices
What does it mean if a processor is "x-bit"? (e.g. 64-bit)
The word length the processor can handle
What is the job of the PC?
Tracks the memory address of the next instruction to be executed
How is a row selected in a memory chip?
Using an address decoder
State the disadvantages of polled I/O
Wastes CPU time and consumes power Polling can be slow when interleaved with other tasks
Define an "overflow" in an addition
When the result generated is too large to fit on the bus
What is a "don't care condition" on a Karnaugh map?
Where the combination of inputs cannot happen, so an x is placed in the value square. The x can be treated as a 1
How can a hex value be used in assembly?
prefix of $
How can a binary value be used in assembly?
prefix of %
State De Morgan's law
¬(AB) = ¬A + ¬B ¬(A+B) = ¬A . ¬B
What symbol denotes XOR in a boolean expression?
⊕
