CS 330 Test 2

ZERO

Don't worry too much about this one. The basic idea is that it takes every input from the 32 1-bit ALUs and puts them through a NOR gate. So only if every result bit is a 0, then the ZERO operation will get flagged as true=1. Otherwise, if there is a single 1 in as any result bit, the ZERO operation will result in false=0.

AND

In order to do the AND operation, the ALU only needs an AND gate that feeds into the mux before the output. Takes A and B as the two inputs. Operation (mux selector) would equal 00 for this operation.

OR

In order to do the OR operation, the ALU only need an OR gate that feeds into the mux before the output. Takes A and B as the two inputs. Operation would equal 01 for this operation.

addi

add immediate: does the same functionally as the add call, but instead of adding two registers together, it adds an immediate to a register

add

add: a operation that adds two values together and copies the result into a given register add $t0, $t1, $t2 (adds values from t1 and t2 and stores in t3)

Verilog operators

arithmetic: + = * / relational: < > <= >= == != bit shifting: << >> conditional: ...?...:... (ex. x=(y > 5) ? w : z means "if y>5 is true then x=w, else x=z")

sll

bitwise shift left: shifts bitwise value left sll $s0, $s1, 2 //shifts it by two (works the same for srl, going right, and ,or, nor)

beq

branch if equal: if two registers are equal, it will branch to another section beq $t0, $t1, print (works the same for bne, bge, ble, etc.)

Declaring reg

ex. [31:0] S0 This declares a register variable with the name S0, with 32 bits, again the highest bit being the MSB while the lowest is the LSB.

Declaring wires

ex. [3:0] out This declares a wire variable named out that consists of 4 bits, bit 3 being the MSB while bit 0 is the LSB.

initial block

executes before the circuit begins to execute; used to initialize variables

Always Block

executes continuously; used to describe combinational circuits. Assign statement is a shorthand way to write an always block. ex. assign A <= B&C; ----> always @(B,C) A <= B&C;

lw

load word: this copies a value stored in memory to a given register lw $t0, hello_world of lw $t0, 4(hello_world) //this stores the value with an offset of 4 bytes (address+4)

Verilog

Verilog is a hardware description language that expresses the behavior of circuits.

slt

set on less than: compares the value off two registers and returns 1 or 0 to another register, 1=true 0=false slt $t0, $t1, $t2 //if t1 is less than t2, t0 = 1

sw

store word: stores a value into memory address mapped by the label sw $t0, label

MIPS

$t0 - $t9 and $s0 - $s7 are all registers that effectively act as variables in MIPS .data section - the section where data is stored to memory, similar to variables in higher level languages. Here you can declare things such as array: .space 256 or "strings" like string: .asciiz "hello world". .text section - the section that contains instructions and program logic. MIPS executes instructions sequentially for the most part.

The 7 ALU operations

1. AND 2. OR 3. ADD 4. SUBTRACTION 5. NOR 6. SLT 7. ZERO

Structure of a Verilog Module

1. Header - declares the module: name, input, and outputs 2. IO declarations 3. Statements that describe the behavior of the circuit. ex. module equals (A,B,out) input [31:0] A,B; output out; always @(A,B) begin if (A==B) begin out <=1; end; else begin out <= 0; end end; end module;

Operation Control Lines

AND = 0000 OR = 0001 ADD = 0010 SUBTRACT = 0110 SLT = 0111 NOR = 1100

ALU

Arithmetic Logic Unit which performs 7 operations

Two Kinds of Assignment

Continuous Assignment: uses <= ; evaluated and updated whenever an input operand changes. procedural assignment: uses = ; executes only when the flow of control indicates to do so. In a block, they execute sequentially.

Quine-McCluskey Algorithm

An algorithm used to find the minimum circuit size to compute a given function ex. wxy+w~xy+wx~y+w~x~y+~wxy For the first section, we take all the groups separated by OR and list them. For each group we mark literals with 1 and negated literals as 0. We then count how many 1s they contain. 1. wxy 111 3 2. w~xy 101 2 3. wx~y 110 2 4. w~x~y 100 1 5. ~wxy 011 2 For the second section, we look to the first and find the groups that share amount of 1s and only differ by 1 bit in the same location. We mark the 2 down and write down a new grouping with the opposite literals taken out. We follow the convention of the first section by marking whether or not any given literal is negated or not with 1s and 0s. We indicate eliminated literals with a dash. (1,2) wy 1-1 (1,3) wx 11- (1,5) xy -11 (3,4) w~y 1-0 (2,4) w~x 10- We continue this process of elimination until we no longer can. We continue to look for bits in the same position that differ. ((1,2),(3,4)) w // we would normally write down the match at 3,4 and // 2,4 but we have already produced a 'w' and we don't care about repeats. Finally, when we can no longer reduce the terms any further, we create a table. On the top of the table we write down all the individual groups or terms that we started with. On the left side of the table, we write down all the groups or terms that we could not reduce any further (this can be tricky, since some of these could be found in prior sections, so look further back than just the last one). Once we have created the table, we look to see for each of the fully reduced terms on the left if they appear in any of the groups on top. If so, we indicate this with an X. For us to consider them to have appeared, we are only focused on the parts of the original terms that match the fully reduced one. For instance, if an original term was xyz and the fully reduced term we are checking is only w, we would consider that to be a match and mark it with an X, since w does appear as normal. If either w appeared as ~w, it would not match. wxy w~xy wx~y w~x~y ~wxy ------------------------------------------------ w | X X X X xy | X X Since every term on the top has an X below it, we now know that the entire equation can be reduced to the terms on the left. Therefore, w + xy is the minimal expression. Sidenote: if one of the terms on top had no X below it, we would simply add it to the minimal expression.

Concatenation

Constant values can be concatenated with {}. ex. {1`b0,31`b1} = 00000000000000000000000000000001 (a 32 bit number) Furthermore, a value can be concatenated x number of times using this format: {x{bitfield}} ex. {8{4`hF}} = 4`hF concatenates with itself 8 times. Since 4`hF = 1111, this too becomes a 32 bit number. Bit ranges can also be specified using [:] ex. if A is 32`hABCDEF and B is 32`h12345678 then {A[31:16], B[15:0]} = ABCDE...45678.

Constant values

Constant values have a size and value; the size is expressed in decimal while the value can be expressed in binary(b), decimal(d), or hex(h). The format of constant variable declarations is [size]`[format][value] ex. 3`b010 expresses a constant of size 3 with the format of binary and the value of 010

SLT

In order to find out if A is less than B (or vice versa) we would simply need to subtract the two and see if the resulting number is less than zero. Generally speaking, the result from a SLT operation will be the sign bit of the result of A-B. If A < B, the result will be negative. All bit except for the Lsb are set to 0, and the output of the Lsb is the result of SLT. For two's complement, which is what the ALU generally calculates, the Msb is the sign bit which gets sent to the Lsb in the case of SLT. Rember, if the Most Significant Bit of an integer is 1, then it is a negative number, a positive number if it is 0.

Overflow Detection

In the ALU there is an overflow output. This is really for exactly what it sounds like. For instance, if you decide to add 2 numbers where a bit continues to carry until it no longer can, the overflow detection catches it.

NOR

Once we've set up the ALU for the SUBTRACTION and ADD operators, the implementation of NOR is very easy. We simply add a mux to the A input that inverts every bit of A, the exact same one we use to invert B. By inverting both A and B and feeding both into the AND gate, we get the NOR operation.

Verilog Specific operators

Suppose A is a register: &A applies bitwise and to every bit in A |A applies bitwise or to every bit in A ^A applies bitwise exclusive or to every bit in A

ADD

The ALU requires the implementation of the full adder for the ADD operation, including a new input, Cin, as well as creating a new output, Cout. The operation would be equal to 10 for this operation.

SUBTRACTION

The ALU uses the full adder in order to do subtraction on A and B. However, B gets fed through a mux with the selector called Binvert. If this selector is set to 1, B gets inverted, so instead of the full adder performing A+B+0, the full adder would instead add A+~B+1 which is equivalent to A-B. You'll notice both equations add either 0 or 1, which is the value of the value, CarryIn. So if we wanted the ALU to perform subtraction, we would set the CarryIn to 1 which would increase the entire sum by 1. ~B+1 is exactly how one would negate a two's complement integer, by negating every bit of B and then adding 1. So effectively, we are adding A to a negated B.

Two Verilog Data Types

Wire: A wire specifies an input or output to a combinational circuit. Reg: a reg holds a bit value which can vary over time, depending on other values in the program.

accessing arrays

firstly, in the .data section you must declare some space in memory for the "array". ex. array: .space 40 lets say $t0 = i, $s7 = la array[] sll $t5, $t0, 2 // $t5 = 4*i add $t5, $t5, $s7 // $t5 = 4*i+address //to access some element, you must calculate 4*i+address now that you have that, you can access this element of the array and do what you'd like with it. sw $some register, 0($t5) //already has offset calculated in, doesn't need another. All of this only works if i is known, so you can access the ith element.

loops

generally for any loop, you will use the j instruction to continue calling some section and some branch instruction to break out of the loop.

j

jump: simply jumps to a certain section of instructions j print

Printing Hello World

la $a0, hello_world //this loads the address of the string hello world from memory to the argument 0 register li $v0, 4 //this loads immediate to the v register (syscall value 4) syscall //this prints the string hello world

printing

la $a0, word li $v0, whatever syscall number it is syscall //works for stored strings and such lw $a0, 0($t0) li $v0, syscall number syscall //works for printing values of registers

For Loops

lets say register $s0 = i and $s1 = n //for (int i = 0; i < n; i++) forloop: bge $s0, $s1, end //some instructions would go here add $s0, $s0, 1 // equivalent to i++ j forloop

move

move: copies the value of one register to another move $t0, $t1 //copies the value of t1 to t0

variables

variable names must begin with a letter and only contain numbers, letters, underscores, or dollar signs.