cs270

Complete the following PUSH routine. Assume the stack grows toward lower numbered addresses, R6 is the stack pointer and each element of the stack requires three memory locations. ADD R6, R6, _____ STR R0, R6, #0 #-1 #1 #3 #-3

#-3

In a 16-bit address space A[15:0], if A[15:10] = 111111, were allocated to I/O device registers (i.e. most significant 6 bits of all addresses related to I/0 are 111111) The number of memory mapped I/O addresses is: 4096 2048 1024 8192

1024

Bit _____ of the Jump to Subroutine instruction specifies which addressing mode to use to determine the target address 0 5 14 15 11

11

The interrupt enable bit in the KBSR and the DSR is at what bit position? 15 14 0 1

14

In KBSR, bit ___ is the interrupt enable bit. If the bit is ___ , then interrupt-driven I/O is enabled.

14 set

What does the PC contain on executing JSR FOO in the following code fragment: .ORIG x3000 JSR FOO ADD R0,R4,R2 FOO ADD R0,R0,#1 RET x3002 x2fff x3003 x3001

3001

The execution of the JSR instruction at location x4202, causes R7 to be loaded with: x4200 x4202 x4201 x4203

4203

The execution of the JSR instruction at location x4202, causes R7 to be loaded with: x4201 x4200 x4202 x4203

4203

The execution of the JSR instruction at location x4202, causes R7 to be loaded with: x4201 x4203 x4200 x4202

4203

The instruction TRAP x23 at location x4232, causes R7 to be loaded with: x4233 x4232 contents of x4232 contents of x4233

4233

How many priority levels does the LC-3 processor have? 8 4 16 2

8

A function P calls a function Q which uses 3 local variables. At the beginning of Q, the following code is needed: A:ADD R6, R6, #-1; space for return value ADD R6, R6, #-1 STR R7, R6, #0; Push return address ADD R6, R6, #-1; STR R5, R6, #0; Push caller's frame pointer ADD R5, R6, #-1; Set new frame pointer ADD R6, R6, #-3; space for Q's local variables B:ADD R6, R6, #-1; space for return value ADD R6, R6, #-1 STR R7, R6, #0; Push return address ADD R6, R6, #-1; STR R5, R6, #0; Push caller's frame pointer ADD R5, R6, #-1; Set new frame pointer ADD R6, R6, #-2; space for Q's local variables C:ADD R6, R6, #-1; space for return value ADD R6, R6, #0 STR R7, R6, #-1; Push return address ADD R6, R6, #-1; STR R5, R6, #0; Push caller's frame pointer ADD R5, R6, #-1; Set new frame pointer ADD R6, R6, #-3; space for Q's local variables D:ADD R6, R6, #-1; space for return value ADD R6, R6, #-1 STR R7, R6, #0; Push return address ADD R6, R6, #-1; STR R5, R6, #0; Push caller's frame pointer ADD R5, R6, #-2; Set new frame pointer ADD R6, R6, #-3; space for Q's local variables

A

A function X calls function Y, using the activation record format used in our text. It involves, among other things, a sequence of PUSHes and POPs. The sequence is: A:X: Pushes arguments. Beginning of Y: Pushes R7, R5. End of Y: Pops local variables, R5, R7. X: Pops return value, arguments B:X: Pushes arguments. Beginning of Y: Pushes R7. End of Y: Pops local variables, R7. X: Pops return value, arguments C:X: Pushes arguments, R7. Beginning of Y: Pushes R5. End of Y: Pops local variables, R5, R7. X: Pops return value, arguments D;X: Pushes arguments. Beginning of Y: Pushes R7, R5. End of Y: Pops local variables, R5. X: Pops R7, return value, arguments

A

The calling convention should be such that every function is caller-independent. What does that mean? A function should be callable from any memory. A function should be callable from any function. A function should be callable from any register. A function should be callable from any object.

A function should be callable from any function.

A push of the value in R3 onto the run-time stack in LC-3 requires which two commands? ADD R5, R5, #-1 STR R3, R5, #0 ADD R6, R6, #-1 LDR R3, R6, #0 ADD R6, R6, #-1 STR R3, R6, #0 ADD R5, R5, #-1 LDR R3, R5, #0

ADD R6, R6, #-1 STR R3, R6, #0

Fill in the blanks: INPUT LDI R5, [ Select ] BRzp INPUT LDI R0, [ Select ] OUTPUT LDI R2, B BRzp OUTPUT STI R0, [ Select ] BR FOO A .FILL xFE06 ;address of DDR B .FILL xFE04 ;address of DSR C .FILL xFE02 ;address of KBDR D .FILL xFE00 ;address of KBSR

D C B A

In the LC-3, the two device registers for the monitor are the ___ and the ___ . (3 uppercase letters)

DSR DDR

What does the following code do: LEA R1, PROMPT L1 LDR R0, R1, #0 BRz FOO ;where FOO is some other routine. L2 LDI R3, DSR BRzp L2 STI R0, DDR ADD R1, R1, #1 BR L1 DSR .FILL xFE04 DDR .FILL xFE06 PROMPT .STRINGZ "Hello World" Goes in an infinite loop till the user enters the string "Hello World" Branches off to FOO without doing anything Displays the string "Hello World" Prints the string "Hello World" backwards

Displays the string "Hello World"

What is the output of the following program? .ORIG x3000 ST R0, x3007 LEA R0, LABEL TRAP x22 TRAP x25 LABEL .STRINGZ "FUNKY" LABEL2 .STRINGZ "Hello World" .END FUNKY Hello World FUNKY Hello World Hello World FUNKY

FUNKY

A stack is a First In First Out data structure True False

False

After the completion of the input service routine, the ASCII code of the character typed is available in register R7. True False

False

An I/O device can signal the microprocessor when it needs to interact with it. This form of interaction is known as polling. True False

False

Bits [11:0] of the RET instruction specify the address to return to. True False

False

Computers that map I/O device registers to memory locations and use the same instructions to access I/O as they do to access memory are said to use special input/output instructions. True False

False

In a stack implemented in memory with a stack pointer, the data entries move after each operation performed on the stack. True False

False

In the LC-3, when a key on the keyboard is pressed, KBDR holds the 2's complement representation of that key. True False

False

Polling the I/O device is more efficient than interrupt driven I/O. True False

False

Some symbol table entries are created in the second pass of a two-pass assembler. True False

False

The EXECUTE phase of the instruction cycle is accompanied by a test for the interrupt signal. True False

False

The LC-3 uses special input/output instructions to communicate with I/O devices. True False

False

The TRAP instruction stores the address of the instruction following the TRAP instruction in R0 before loading the PC with the starting address of the service routine. True False

False

The declaration of a variable as a struct is one of the constructs of structured programming. True False

False

What does this instruction do? LEA R5, LAB It loads into R5 the address of the location with label LAB It loads into R5 the contents of the location with label LAB The instruction is incomplete, it needs another source register. It loads the contents of R5 into the location with label LAB

It loads into R5 the address of the location with label LAB

In LC3, the instruction RET can be called by another name. It is JSRR R7 RTI .END JMP R7

JMP R7

In the LC-3, the two device registers for the keyboard are the ___ and the ____. (Four uppercase letters)

KBDR KBSR

To pop the value off the run-time stack and put it into register 3, we need which of the following two commands? LDR R3, R6, #0 ADD R6, R6, #1 STR R3, R6, #0 ADD R6, R6, #1 STR R3, R6, #0 ADD R5, R5, #1 LDR R3, R6, #0 ADD R5, R5, #1

LDR R3, R6, #0 ADD R6, R6, #1

According to the lecture slides, when an interrupt happens in the LC3, what registers are pushed onto the supervisor stack to save the state of the currently executing program? Only PC. The interrupt service routine need to save the rest of the Processor State. PSR (containing P, PL and N,Z,P fields), PC and all registeres PSR (containing P, PL and N,Z,P fields) and PC Nothing needs to be saved, because during an interrupt the processor does not do anything.

PSR (containing P, PL and N,Z,P fields) and PC

The assembler will recognize TRAP x22 as the following string as well: IN SQRT HALT PUTS

PUTS

On completion of the standard LC-3 input service routine, register _______ contains the ASCII code of the character typed in. R1 IR R7 R0 PC

R0

In the following program, what would the contents of R0 and R6 right before HALT? (This question is not using the stack protocol we have discussed just pushing and popping from a basic stack) ;Calling program. ORIG x3000 LD R6, STACK LD R0, A JSR PUSH LD R0, B JSR PUSH JSR POP LD R0, C JSR PUSH JSR POP JSR POP HALT; subroutinePOP LDR R0, R6, #0 ; The actual "pop." ADD R6, R6, #1 ; Adjust stack pointer BRnzp success_exit PUSH ADD R6, R6, #-1 ; Adjust stack pointer STR R0, R6, #0 ; The actual "push" success_exit RET STACK .FILL x301b A .FILL x03 B .FILL x04 C .Fill x05 .END

R0 = x03 R6 = x301B

If R6 is the stack pointer, and the stack grows towards zero, what is wrong with the following pop routine: LDR R0, R6, #0 ADD R6, R6, #-1 R6 should be incremented twice, not once. Nothing is wrong. R6 should be incremented, not decremented. The value of R6 is written to R0, not the contents of the memory location pointed to by R6.

R6 should be incremented, not decremented.

The test for an interrupt signal is done after which phase of the instruction cycle? EXECUTE OPERAND EVALUATION DECODE STORE RESULT

STORE RESULT

If the program does not check DSR before writing to DDR, the following can happen: Everything will work correctly The program will display some characters multiple times. No character will be displayed. Some characters may not be displayed on the monitor.

Some characters may not be displayed on the monitor

Interrupt-driven I/O is more efficient that polling because: The statement is wrong. Polling is more efficient than interrupt-driven I/O. The processor can perform other tasks instead of constantly being in a loop checking to see if the status bit has changed. Interrupts to the processor take less time than polling loops. Polling consists of interrupt-driven I/O plus additional overhead.

The processor can perform other tasks instead of constantly being in a loop checking to see if the status bit has changed

A processor can either be in the "user" mode or the "supervisor" mode. When an interrupt occurs, The processor will be in the supervisor mode while the interrupt service routine is being executed. The processor will be in the supervisor mode while the interrupt service routine is being executed, only if the interrupted program was in the user mode. An interrupt will always cause a switch to the opposite mode. The interrupt service routine can be either in the user mode or the supervisor mode.

The processor will be in the supervisor mode while the interrupt service routine is being executed.

If the input service routine reads KBDR without checking the ready bit of KBSR, the following can happen: The program could read the same key multiple times. The program will drop some characters. Everything will work correctly. No characters will be entered.

The program could read the same key multiple times

R6 is the stack pointer. What are the contents of R0 after this operation: LDR R0, R6, #0 The value of the top of the stack 0 The value of the bottom of the stack The stack pointer

The value at the top of the stack

A device register holds either the data being transferred between the I/O device and the computer, or information about the I/O device. True False

True

Changing R7 without saving its contents during a service routine is problematic as it destroys the linkage back to the initiating program. True False

True

If R6 is the stack pointer and each element in the stack occupies two memory locations, a push operation on the stack requires that R6 be decremented by 2. True False

True

If the I/O service routine writing to the monitor does not check DSR before writing to DDR, some characters may not be displayed on the monitor. True False

True

If the keyboard hardware does not check the KBSR before writing to the KBDR, the processor might read some characters that were typed twice. True False

True

In the LC-3, the user program invokes the OS to perform an I/O operation using the TRAP command. True False

True

The .blkw pseudo-op sets aside some number of memory locations in the program space, probably to be used later for storing values. True False

True

The JSR instruction can only jump to a subroutine, which is within +1024 or -1023 locations of the JSR instruction. True False

True

The LC-3 has two device registers to handle input from the keyboard. The keyboard data register (KBDR) and the keyboard status register (KBSR). True False

True

The Location Counter is a device that is used to translate an assembly language program but not used to execute that program. True False

True

The System Control Block or the Trap Vector Table is a set of memory locations which contain the starting addresses of the service routines. True False

True

The only difference between JSR and JSRR is the addressing mode used for evaluating the starting address of the subroutine. True False

True

The return address at a recursive function call (e.g., when Fibonacci calls Fibonacci) is always the same. True False

True

The stack pointer keeps track of the first element to be popped off the stack. True False

True

To enable interrupt-driven I/O for the keyboard in the LC-3, bit 14 of the KBSR should be set. True False

True

We can evaluate any arithmetic expression using the run-time stack. True False

True

When using a stack for storing data related to a function call (return value, return address, local variables, etc.) if function foo() calls function bar() a variable local to bar() will have an address that is lower than a local variable in foo(). True False

True

What is wrong with the code fragment: .ORIG x3000 AND R0,R0, #0 JSR FOO ADD R2,R0, #2 ADD R3,R2, #0 TRAP x21 FOO ADD R2,R2,#9 AND R7,R7,#1 RET .END We are modifying the contents of register R7. This destroys the linkage back to the calling routine Nothing is wrong In the instruction ADD R2, R2, #9 the immediate value 9 is to large to be encoded in the instructions TRAP x21 will not work after a subroutine call.

We are modifying the contents of register R7. This destroys the linkage back to the calling routine

The _____ produces an object module from the code written in the LC-3 Assembly Language. The ____ combines one or more object modules to produce a single binary executable.

assembler linker

An LC-3 instruction ADD R1,R2, #45 produces an error. It will be caught at assembly time link time run time

assembly time

An LC-3 instruction ADD R6,R7,R8 produces an error. It will be caught at assembly time link time compile time

assembly time

The term ___________ denotes the case where the called program saves the contents of registers whose contents will be changed during the invocation of the called program. callee save caller save

callee save

The ________ construct is appropriate when one of two tasks is to be performed, depending on the state of some variable.

conditional

What does the following program do: .ORIG x3000 TRAP x20 TRAP X21 echoes the character pressed and halts does nothing echoes the character typed on the keyboard to the monitor halts once a key is pressed

echoes the character typed on the keyboard to the monitor

A __________ is a collection of programs/functions that can be used by application programmers to perform frequent tasks. library subroutine TRAP instruction assembly file

library

Which instruction performs the exact same function as JMP: BRnzp BRnp none BRnz

none

Which of the following are parts of an assembly language instruction? number of cycles required to execute the instruction operands comment label opcode

operands comment label opcode

The following example reads in a character from the keyboard. Is it interrupt driven I/O or polling? START LDI R1, A BRzp START LDI R0, B BR FOO ;go somewhere else once done A .FILL xFE00 ;address of KBSR B .FILL xFE02 ;address of KBDR polling interrupt-driven neither polling or interrupt-driven both answers

polling

The constructs of structured programming are recursive logical sequential iterative conditional

sequential iterative conditional

The instruction TRAP x25 causes the PC to be loaded with the memory address: the contents of x0025 x0025 x2500 x0250

the contents of x0025

In the KBSR, an interrupt signal is generated by the AND of: the ready bit and the interrupt-enable bit the start and stop bits the start bit and the interrupt-enable bit the ready bit and the start bit

the ready bit and the interrupt-enable bit

Fill in the blanks: A trap instruction finds the address of the trap service routine from the System Control Block using the____ , whereas JSR obtains the address of the subroutine using the ____ in the instruction.

trap vector pc offset

If bit 15 in the DSR is set to 1, the microprocessor can transfer an ASCII code to display on the monitor. True False

true

In the following program, what would the contents of R0 and R6 right before HALT? ;Calling program .ORIG x3000 LD R6, SPINT LD R0, A JSR Push LD R0, B JSR Push JSR Pop LD R0, C JSR Push JSR Pop JSR Pop HALT ; ;Subroutine Pop LDR R0, R6, #0 ; The actual "pop." ADD R6, R6, #1 ; Adjust stack pointer BRnzp exit ; Push ADD R6, R6, #-1 ; Adjust stack pointer STR R0, R6, #0 ; The actual "push" exit RET ; SPINT .FILL x301b A .FILL x03 B .FILL x04 C .Fill x05 .END x0003 in R0 and x301A in R6. x0003 in R0 and x301B in R6. x0004 in R0 and x301A in R6. x0005 in R0 and x301B in R6.

x0003 in R0 and x301B in R6

Assume that the stack grows towards zero, the stack pointer is R6 and contains x4000. What are the contents of R6 after the following operations: push 5 push 4 push 3 push 2 pop pop x3FFE x3FFF x4000 x4002

x3FFE

If R4 contains x5000 and the JSRR instruction is stored in x4002, the execution of JSRR R4 causes R7 to be loaded with: x4003 x4001 x5001 x5000

x4003

If R3 contains x5000 and the JSRR instruction is stored in x4000, the value of the PC after execution of JSRR R3 is: x5000 x4000 the contents of memory location x5000 the contents of memory location x4000

x5000