Digital Electronics - Section 1

If memory chip size is 256 x 1 bits, the number of chips required to make 1 k byte memory is A. 8 B. 12 C. 24 D. 32

(1024 x 8)/(256 x 1 ) = 32.

2's complement of binary number 0101 is A. 1011 B. 1111 C. 1101 D. 1110

A

A 4 bit parallel type A/D converter uses a 6 volt reference. How many comparators are required and what is the resolution in volts? A. 0.375 V B. 15 V C. 4.5 V D. 10 V

A

A counter type A/D converter contains a 4 bit binary ladder and a counter driven by a 2 MHz clock. Then conversion time A. 8 μ sec B. 10 μ sec C. 2 μ sec D. 5 μ sec

A

ECL has high switching speed because the transistors are A. switching between cutoff and saturation regions B. switching between cutoff and active regions C. switching between active and saturation regions D. none of the above

B High speed is obtained because saturation state is avoided.

A mod 4 counter will count A. from 0 to 4 B. from 0 to 3 C. from any number n to n + 4 D. none of the above

B Mod 4 counter has 4 states, 0 to 3.

A current tracer responds to A. steady current only B. pulsating current only C. both pulsating and steady current D. none of the above

B The indicator of current tracer glows when its tip is held over a pulsating current path.

Out of latch and flip flop, which has clock input? A. Latch only B. Flip flop only C. Both latch and flip flop D. None

B This the main difference between latch and flip-flop. Only flip-flop has clock input.

In a JK master slave flip flop A. master is clocked when clock is low B. slave is clocked when clock is high C. master is clocked when clock is high and slave is clocked when clock is low D. master is clocked when clock is low and slave is clocked when clock is high

C

In a positive edge triggered D flip flop A. D input is called direct set B. Preset is called direct reset C. Present and clear are called direct set and reset respectively D. D input overrides other inputs

C

The number of unused states in a 4 bit Johnson counter is A. 2 B. 4 C. 8 D. 12

C

A divide by 78 counter can be obtained by A. 6 numbers of mod-13 counters B. 13 numbers of mod-6 counters C. one mod-13 counter followed by mod-6 counter D. 13 number of mod-13 counters

C Modulus 13 x modulus 6 = modulus 78.

A NAND gate has: A. active-LOW inputs and an active-HIGH output. B. active-LOW inputs and an active-LOW output. C. active-HIGH inputs and an active-HIGH output. D. active-HIGH inputs and an active-LOW output.

D

A three state switch has three outputs. These are A. low, low and high B. low, high, high C. low. floating, low D. low, high, floating

D

In 2's complement representation the number 11100101 represents the decimal number A. +37 B. -31 C. +27 D. -27

D

The number of counter states which an 8 bit stair step A/D converter has to pass through before conversion takes place is equal to A. 1 B. 8 C. 255 D. 256

D

Which of these are two state devices? A. Lamp B. Punched card C. Magnetic tape D. All of the above

D

Assertion (A): CMOS devices have very high speed. Reason (R): CMOS devices have very small physical size and simple geometry. A. Both A and R are correct and R is correct explanation of A B. Both A and R are correct but R is not correct explanation of A C. A is true, R is false D. A is false, R is true

D CMOS has high packing density but low speed.

An 8 bit data is to be entered into a parallel in register. The number of clock pulses required is A. 8 B. 4 C. 2 D. 1

D In a parallel in register only one pulse is needed to enter data.

A device which converts BCD to seven segment is called A. encoder B. decoder C. multiplexer D. none of these

B

A full adder can be made out of A. two half adders B. two half adders and a OR gate C. two half adders and a NOT gate D. three half adders

B

DeMorgan's first theorem shows the equivalence of A. OR gate and Exclusive OR gate B. NOR gate and Bubbled AND gate C. NOR gate and NAND gate D. NAND gate and NOT gate

B

In a 3 input NAND gate, the number of states in which output is 1 equals A. 8 B. 1 C. 6 D. 5

B

In register index addressing mode the effective address is given by A. index register value B. sum of the index register value and the operand C. operand D. difference of the index register value and the operand

B

Minimum number of 2-input NAND gates required to implement the function F = (x^ + y^) (Z + W) is A. 3 B. 4 C. 5 D. 6

B

Parallel adder is A. sequential circuit B. combinational circuit C. either sequential or combinational circuit D. none of the above

B

The first machine cycle of an instruction is always A. a memory read cycle B. a fetch cycle C. a input/output read cycle D. a memory write cycle

B

The total number of input words for 4 input OR gate is A. 20 B. 16 C. 12 D. 8

B

Which of the following finds application in pocket calculators? A. TTL B. CMOS C. ECL D. Both (a) and (c)

B

A carry look ahead adder is frequently used for addition because A. it costs less B. it is faster C. it is more accurate D. is uses fewer gates

B In look ahead carry adder the carry is directly derived from the gates when original inputs are being added. Hence the addition is fast. This process requires more gates and is costly.

In which counter does the maximum frequency depend on the modulus? A. Synchronous B. Ripple C. Both synchronous and ripple D. Neither synchronous nor ripple

B Since propagation delays of all flip-flops are added in ripple counter, the maximum frequency depends on the number of flip-flops which depends on modulus.

A 3 input NAND gate is to be used as inverter. Which of the following will give better results? A. The two unused inputs are left open B. The two unused inputs are connected to 0 C. The two unused inputs are connected to 1 D. None of the above

C

A universal shift register can shift A. from left to right B. from right to left C. both from left to right and right to left D. none of the above

C

Assertion (A): A multiplexer can be used for data routing. Reason (R): A multiplexer has one input and many outputs. A. Both A and R are correct and R is correct explanation of A B. Both A and R are correct but R is not correct explanation of A C. A is true, R is false D. A is false, R is true

C

Assertion (A): The output of a NOR gate is equal to the complement of OR of input variables. Reason (R): A XOR gate is a universal gate. A. Both A and R are correct and R is correct explanation of A B. Both A and R are correct but R is not correct explanation of A C. A is true, R is false D. A is false, R is true

C

In a positive edge triggered JK flip flop A. High J and High K produce inactive state B. Low J and High K produce inactive state C. Low J and Low K produce inactive state D. High J and Low K produce inactive state

C

The output of a half adder is A. SUM B. CARRY C. SUM and CARRY D. none of the above

C

The resolution of an n bit DAC with a maximum input of 5 V is 5 mV. The value of n is A. 8 B. 9 C. 10 D. 11

C

he no. of comparators required in a 3 bit comparator type ADC is A. 2 B. 3 C. 7 D. 8

C

BCD input 1000 is fed to a 7 segment display through a BCD to 7 segment decoder/driver. The segments which will lit up are A. a, b, d B. a, b, c C. all D. a, b, g, c, d

C 1000 equals decimal 8 Therefore all segments will lit up.

A decade counter skips A. binary states 1000 to 1111 B. binary states 0000 to 0011 C. binary states 1010 to 1111 D. binary states 1111 to higher

C A decade counter counts from 0 to 9. It has 4 flip-flops. The states skipped are 10 to 15 or 1010 to 1111.

Assertion (A): A demultiplexer can be used as a decoder. Reason (R): A demultiplexer can be built by using AND gates only. A. Both A and R are correct and R is correct explanation of A B. Both A and R are correct but R is not correct explanation of A C. A is true, R is false D. A is false, R is true

C Demultiplexer requires NOT gates also in addition to AND gates.

Which of the following is error correcting code? A. EBCDIC B. Gray C. Hamming D. ASCII

C Hamming code is widely used for error correction.

Assertion (A): TTL is a very popular logic in SSI and MSI category. Reason (R): In Schottky TTL the power dissipation is less than in ordinary TTL. A. Both A and R are correct and R is correct explanation of A B. Both A and R are correct but R is not correct explanation of A C. A is true, R is false D. A is false, R is true

C In Schottky TTL storage time is reduced.

Which display device resembles vacuum tube? A. LED B. LCD C. VF D. None of these

C It is similar to triode.

Assertion (A): Tristate logic is used for bus oriented systems Reason (R): The outputs of a tristate logic are 0, 1 and indeterminant. A. Both A and R are correct and R is correct explanation of A B. Both A and R are correct but R is not correct explanation of A C. A is true, R is false D. A is false, R is true

C Outputs of tristate logic are 0, 1 and high impedance state.

Which of the following is non-saturating? A. TTL B. CMOS C. ECL D. Both (a) and (b)

C Since it is non-saturating, ECL has low propagation delay.

In a 7 segment display, LEDs b and c lit up. The decimal number displayed is A. 9 B. 7 C. 3 D. 1

D

The number of bits in ASCII is A. 12 B. 10 C. 9 D. 7

D

The number of address lines in EPROM 4096 x 8 is A. 2 B. 4 C. 8 D. 12

D 2^12 = 4096

A 4 input AND gate is equivalent to A. 4 switches in parallel B. 2 switches in series and 2 in parallel C. three switches in parallel and one in series D. 4 switches in series

D All the switches have to be closed so that the circuit can be made. In AND gate all the inputs have to be high for output to be high.

An 8 bit binary number is to be entered into an 8 bit serial shift register. The number of clock pulses required is A. 1 B. 2 C. 4 D. 8

D In serial shift register one pulse is needed to store each bit.

In the expression A + BC, the total number of minterms will be A. 2 B. 3 C. 4 D. 5

D The min terms are A^BC + ABC + AB^ C^ + AB^C + ABC^.

A half adder adds A. 2 bits B. 3 bits C. 4 bits D. 2 or 3 bits

A

A ring counter with 5 flip flops will have A. 5 states B. 10 states C. 32 states D. infinite states

A

In a D latch A. data bit D is fed to S input and D^ to R input B. data bit D is fed to R input and D^ to S input C. data bit D is fed to both R and S inputs D. data bit D^ is not fed to any input

A

It is desired to display the digit 7 using a seven segment display. The LEDs to be turned on are A. a, b, c B. b, c, d C. c, d, e D. a, b, d

A

Which of the following are included in the architecture of computer? Addressing mode, design of CPU Instruction set, data format Secondary memory, operating system Select the correct answer using the codes given below: A. 1 and 2 B. 2 and 3 C. 1 and 3 D. 1, 2 and 3

A

Which of the following is susceptible to race condition? A. R-S latch B. D latch C. Both R - S and D latches D. None of the above

A

In a ripple counter, A. whenever a flip flop sets to 1, the next higher FF toggles B. whenever a flip flop sets to 0, the next higher FF remains unchanged C. whenever a flip flop sets to 1, the next higher FF faces race condition D. whenever a flip flop sets to 0, the next higher FF faces race condition

A In a ripple counter the effect ripples through the counter.

Using the same flip flops A. a synchronous flip flop can operate at higher frequency than ripple counter B. a ripple counter can operate at higher frequency than synchronous counter C. both ripple and synchronous counter can operate at the same frequency D. can not determine

A In a synchronous counter clock pulses are applied to all flip-flops simultaneously. Hence minimum time delay and high frequency.

The number of inputs and outputs of a full adder are A. 3 and 2 respectively B. 2 and 3 respectively C. 4 and 2 respectively D. 2 and 4 respectively

A Inputs are carry from lower bits and two other bits. Outputs are SUM and CARRY.

In a BCD to 7 segment decoder the minimum and maximum number of outputs active at any time is A. 2 and 7 B. 3 and 7 C. 1 and 6 D. 3 and 6

A Minimum number of outputs when input is decimal 1 and maximum number of outputs when input is decimal 8.

Out of S, R, J, K, Preset, Clear inputs to flip flops, the synchronous inputs are A. S, R, J, K only B. S, R, Preset, Clear only C. Preset, Clear only D. S, R only

A Preset and clear inputs are not applied in any fixed sequence.

n digital circuits Schottky transistors are preferred over normal transistors because of their A. lower propagation delay B. lower power dissipation C. higher propagation delay D. higher power dissipation

A Schottky transistors have low switching time and hence low propagation delay.

Assertion (A): ECL gate has very high speed of operation. Reason (R): Transistors in ECL do not go into saturation region. A. Both A and R are correct and R is correct explanation of A B. Both A and R are correct but R is not correct explanation of A C. A is true, R is false D. A is false, R is true

A Since transistors in ECL do not enter saturation state, switching is fast.

he basic storage element in a digital system is A. flip flop B. counter C. multiplexer D. encoder

A Storing can be done only in memory and flip-flop is a memory element.

The number of digits in octal system is A. 8 B. 7 C. 9 D. 10

A The octal system has 8 digits 0 to 7.