Ch.5 - A Closer Look at Instruction Set Architectures

virtual machine

1. A hypothetical computer. 2. A self-contained operating environment that gives the illusion of the existence of a separate physical machine. 3. A software emulation of a real machine.

resource conflict

A situation in which two instructions need the same resource. May slow down a pipelined CPU.

data dependency

A situation that arises when the result of one instruction, not yet completely executed, is to be used as an operand to a following instruction. May slow down a pipelined CPU.

base/offset addressing

An addressing mode in which an offset is added to a specific base register that is then added to the specified operand to yield the effective address of the data.

self-relative addressing

An addressing mode in which the address of the operand is computed as an offset from the current instruction.

register indirect addressing

An addressing mode in which the contents of a register are used as a pointer to the actual location of the operand.

register addressing

An addressing mode in which the contents of a register are used as the operand.

stack addressing

An addressing mode in which the operand is assumed to be on the system stack.

immediate addressing

An addressing mode in which the value to be referenced immediately follows the operation code in the instruction.

direct addressing

An addressing mode in which the value to be referenced is obtained by specifying its memory address directly in the instruction.

based addressing

An addressing mode that uses a base register (either explicitly or implicitly designated) to store an offset (or displacement), which is added to the operand results in the effective address of the data.

indexed addressing

An addressing mode that uses an index register (either explicitly or implicitly designated) to store an offset (or displacement), which is added to the operand and results in the effective address of the data.

indirect indexed addressing

An addressing mode that uses both indirect and indexed addressing at the same time.

indirect addressing

An addressing mode that uses the bits in the address field to specify a memory address that is to be used as a pointer to the actual operand.

VLIW architecture (Very Long Instruction Word)

An architectural characteristic in which each instruction can specify multiple scalar operations.

load-store architecture

An architecture in which only the load and store instructions of the ISA can access memory. All other instructions must use registers to access data.

accumulator architecture

An architecture that assumes one operand to be in the accumulator without requiring the accumulator to be explicitly referenced in the instruction.

register-memory architecture

An architecture that requires at least one operand to be located in a register and one to be located in memory.

stack architecture

An architecture that uses a stack to execute instructions, where the operands are implicitly found on top of the stack.

expanding opcode

An instruction design that allows the opcode to vary in length, dependent on the number of operands required for the instruction.

orthogonality

An instruction set is said to be ___ if the instructions are independent (there is no overlap in functionality) and consistent (there are no special cases, no special registers, all addressing modes can be used with any data type or instruction type, instructions have the same format, etc.). In the context of programming, an ___ instruction set is one in which all instructions have the same format and register usage and can therefore be used interchangeably. (The choice of register to use is ___ to the choice of instruction).

memory-memory architectures

Architectures that allow an instruction to perform an operation without requiring at least one operand to be in a register.

p-code languages

Languages that are both compiled and interpreted.

prefix notation (Polish)

One of the orderings of operators and operands that places the operators before the operands, such as +23.

infix notation

One of the orderings of operators and operands that places the operators between operands, such as 2 + 3.

reverse Polish notation (RPN)

Postfix Notation; One of the orderings of operators and operands that places the operators after operands, such as 23+.

general-purpose register (GPR) architecture

Registers that can be accessed by the programmer and used for different purposes.

addressing mode

Specifies where the operand for an instruction is located by how the operand is to be interpreted.

big endian

Storing multibyte words in memory with the most significant byte at the lowest address.

little endian

Storing multibyte words with the least significant byte at the lowest address.

effective address

The actual location (in memory) of an operand.

pipelining

The process of breaking down the fetch-decode-execute cycle into smaller steps (pipeline stages), where some of these smaller steps can be overlapped and performed in parallel.

superpipelining

The process of combining superscalar concepts with pipelining by dividing the pipeline stages into many small stages, so that more than one stage can be executed during one clock cycle.

branch prediction

The process of guessing the next instruction in the instruction stream prior to its execution, thus avoiding pipeline stalls due to branching. If the prediction is successful, no delay is introduced into the pipeline. If the prediction is unsuccessful, the pipeline must be flushed and all calculations caused by this miscalculation must be discarded.