Digital Circuit Fundamentals 1
Is common to each stage of the counter
On a synchronous counter, the CLOCK input
If DOWN is pulsed and UP is pulled to V(subCC)
On the LS193 counter, the counter decrements
If UP is pulsed and DOWN is pulled to V(subCC)
On the LS193 counter, the counter increments
Is located in the same position as other TTL DIPs
Pin 1 of a 74LS76 plastic DIP
How do we count pins on a DIP
Pins are counted in a clockwise (CW) direction from a bottom view or counterclockwise (CCW) from a top view (beginning at pin 1)
Compares two 4-bit words on a bit pair basis
The 4-bit comparator
generates a free-running square waveform
The 555 timer CLOCK circuit on the DIGITAL CIRCUIT FUNDAMENTALS 1 circuit board
Are normally high and generate a low active pulse
The CARRY and BORROW outputs of the LS193
Responds to the CLEAR input by placing all true outputs into a momentary low state
The CLEAR input of a free-running ripple counter is momentarily pulled low. The counter
Responds to the SET input by placing all true outputs into a momentary high state
The SET input of a free-running ripple counter is momentarily pulled low. The counter
2, 4, 8, and 16
The frequency division factors of a 4-bit ripple counter are
6.25kHz (100kHz / 16)
The input frequency of a 4-bit ripple counter is 100kHz. What is the frequency at the output of the MSB?
Both of the above (Reset a counter, determine the maximum count value of a counter)
The modulus feedback generated by a comparator can
Change in conjunction with the common CLOCK input
The outputs of a 4-bit synchronous counter
Will change simultaneously
The outputs of a synchronous counter
Requires a positive clock transition
The parallel load function of the serial register
Depends on the response time of the comparator and counter ICs
The pulse width of the CLEAR (A=B) signal
Are correctly related to each other
The waveforms of a typical 4-bit ripple counter
Require a high level on one input and a pulsed level at the other input
To clock the LS193, the CLOCK inputs
Is one less than 9, or 8
When a ripple counter has a modulus of 9 the maximum output count
The eighth count resets the counter
When the NOT Q (BIT4) output of your ripple counter is connected to the CLEAR input of your counter
The counter does not operate
When the Q (BIT4) output of your ripple counter is connected to the CLEAR input of your counter
1111
Word A is specified as 1010. Word B is specified as 0101. The addition of the 2 words yields
We're set high
Your shift register is reset. After the 4th positive clock transition, all 4 outputs are high. You conclude that the SL/SR data inputs
Nibble
4 bits of binary data
Any distribution of serial data
A 4-bit shift register can accept
32
A 5-stage ripple counter provides a frequency or count division of
As the count value decrement from 0000 to 1111
A BORROW output is generated
As the count value increments from 1111 to 0000
A CARRY output is generated
Shift right
A bit or data movement toward QD (from a Less Significant register toward a More Significant register)
Drive the LSB stage of the counter
A clocked ripple counter requires that the clock signal
Does not change the operating mode of a ripple counter
A free-running clock input
The counter stages are daisy-chained
A ripple counter is referred to as a serial counter because
Generates equal groups of outputs, in and out of phase
A ripple counter with complementary outputs
Up and Down
A ripple counter with complementary outputs can count
Will shift through the register until it is removed from the register
A single SL/SR data bit (high)
All of the above (Only if the counter is configured to count up, only if the counter is configured to count down, for both static and dynamic counter clock inputs)
A variable modulus feedback can be used
Add 4-bit words
An adder specified as a two 4-bit word device can
The function of the CLEAR and SET inputs are not affected
As the clock frequency of a ripple counter increases,
The ragtop between the active times of the comparator outputs is altered
As you vary the modulus of your circuit
Ripple Counter is also known as
Binary, Ascynchronous
The input bits
Each sum output of an adder stage is formed by adding
It's respective bit pair
Each sum output of the adder is generated by
Has a value greater than 1
For any individual stage of an adder, the overflow, or carry bit, for that stage is 1 if the output of the preceding stage
Has a value greater than 1
For any individual stage of your adder, the overflow, or carry, bit for that stage is 1 if the output of the preceding stage
16
How many clock cycles are required to generate one complete counting interval of the MSB of a 4-bit ripple counter?
9
If a ripple counter is specified with a modulus (MOD) of $A, the maximum count indication is
Both input words have identical bit patterns
If the A=B output is active, then
All shift register operations are inhibited
If the CLEAR input of your circuit is connected to circuit common
Indicate $A after the LOAD function is activated
If the inputs of the LS193 register equal $A, the outputs of the counter will
Decrease
If the word B value of an adder circuit is decreased from 10 to 5, the time duration of the overflow bit will
16(sub10)
If word B equals 0100 and word A equals 1100, their sum is (1)0000. What is the decimal equivalent?
0000 to 1001, 0000, 0001, and so on
If your circuit has a modulus of 10, its proper up counting sequence is
QA toward QD
If your circuit is configured to right-shift serial data, then the bit stream moves from
Generates an overflow condition and increments the count to 0000
If your counter indicates 1111, the next CLOCK input
Can alternate between right and left
In a given number of CLOCK cycles, the direction of data shift
All of the above (Indicates counter underflow, occurs if the 00000 count of a 5-bit counter is clocked down, generates a pulse width that depends on the CLOCK)
In general, a BORROW ouptut
All of the above (Indicates a counter overflow, occurs if the 11111 count of a 5-bit counter is clocked up, has a pulse width that depends on the CLOCK)
In general, a CARRY output
