CEA201 Unit 5 multi

all of the above

QN=1 Which properties do all semiconductor memory cells share? a. they exhibit two stable states which can be used to represent binary 1 and 0 b. they are capable of being written into to set the state c. they are capable of being read to sense the state d. all of the above

DDR-DRAM

QN=10 ________ can send data to the processor twice per clock cycle. a. CDRAM b. SDRAM c. DDR-DRAM d. RDRAM

DDR2

QN=11 __________ increases the data transfer rate by increasing the operational frequency of the RAM chip and by increasing the prefetch buffer from 2 bits to 4 bits per chip. a. DDR2 b. RDRAM c. CDRAM d. DDR3

DDR3

QN=12 ________ increases the prefetch buffer size to 8 bits. a. CDRAM b. RDRAM c. DDR3 d. all of the above

200 to 600

QN=13 Theoretically, a DDR module can transfer data at a clock rate in the range of __________ MHz. a. 200 to 600 b. 400 to 1066 c. 600 to 1400 d. 800 to 1600

800 to 1600

QN=14 A DDR3 module transfers data at a clock rate of __________ MHz. a. 600 to 1200 b. 800 to 1600 c. 1000 to 2000 d. 1500 to 3000

buffer

QN=15 The ________ enables the RAM chip to preposition bits to be placed on the data bus as rapidly as possible. a. flash memory b. Hamming code c. RamBus d. buffer

RAM

QN=2 One distinguishing characteristic of memory that is designated as _________ is that it is possible to both to read data from the memory and to write new data into the memory easily and rapidly. a. RAM b. ROM c. EPROM d. EEPROM

all of the above

QN=3 Which of the following memory types are nonvolatile? a. erasable PROM b. programmable ROM c. flash memory d. all of the above

SRAM

QN=4 In a _________, binary values are stored using traditional flip-flop logic-gate configurations. a. ROM b. SRAM c. DRAM d. RAM

ROM

QN=5 A __________ contains a permanent pattern of data that cannot be changed, is nonvolatile, and cannot have new data written into it. a. RAM b. SRAM c. ROM d. flash memory

flash memory

QN=6 With _________ the microchip is organized so that a section of memory cells are erased in a single action. a. flash memory b. SDRAM c. DRAM d. EEPROM

Hard errors

QN=7 __________ can be caused by harsh environmental abuse, manufacturing defects, and wear. a. SEC errors b. Hard errors c. Syndrome errors d. Soft errors

Soft errors

QN=8 _________ can be caused by power supply problems or alpha particles. a. Soft errors b. AGT errors c. Hard errors d. SEC errors

SDRAM

QN=9 The _________ exchanges data with the processor synchronized to an external clock signal and running at the full speed of the processor/memory bus without imposing wait states. a. DDR-DRAM b. SDRAM c. CDRAM d. none of the above