Chapter 5 - Flip-Flops True or False Questions #3

A 555 timer can produce an exact 50% duty cycle clocking waveform.

False

A D type latch is able to change states and follow the D input regardless of the level of the ENABLE input.

False

A flip-flop is not considered combinational logic, so a logic probe won't work for debug.

False

A flip-flop's normal starting state when power is first applied to a circuit is always the SET state.

False

Parallel data transfers between 2 different sets of registers requires more than one shift pulse.

False

The Q output of a flip-flop is normally HIGH when the device is in the CLEAR or RESET state.

False

A flip-flop is in the HIGH state when Q = 1.

True

A small internal triangle at the CLK input of a standard flip-flop symbol indicates that inputs can cause changes only when a clock transition occurs.

True

One-shots may be built without external timing components, but normally resistors and capacitors are used to set required timing intervals.

True

Preset and Clear are inputs that are normally asynchronous inputs.

True

The 555 timer can be used in either monostable mode as a one-shot or as an astable multivibrator.

True

The JK flip-flop eliminates the invalid state by toggling when both inputs are high and the clock transitions.

True