Course 102 Day 12

What is the result of two LOW values in an RS/RS Latch? 2 HIGH values?

2 LOW - No change (NC) 2 HIGH - Invalid (unpredictable)

What makes up a quad NAND? Quad NOR?

4 NAND gates, 4 NOR gates

What is the military specification for a TTL? Commercial?

54 - Military code 74 - Commercial/Civilian code You can use a 54 in place of a 74 but not a 74 in place of a 54.

What are asynchronous and synchronous inputs? What is the difference?

Asynchronous - Preset, Clear the overriding signals that take precedence over the synchronous inputs Synchronous - J/K or S/R the signals used when the asynchronous signals are not active

What is a sequential circuit?

Circuit that produces an output when ainput is applied and will remember the output after input has been removed.

What is a combination logic gate?

Combination logic is the combining of 2+ gates

What is the reference voltage level applied to comparator 1? Comparator 2? In a 555 timer.

Comparator 1 - Uses 2/3 Vcc Comparator 2 - Uses 1/3 Vcc

What are the 2 inputs for a D-Type Flip Flop?

D and C (Clock)

What contains all the information you need to know about an IC?

Data Sheet

Inverters do what to the output?

Flip the output

How do you determine if an output will be high/low trigger?

High trigger level - Clock will be high level activated (Only changes during high levels will change waveform) Low trigger level - Clock will be low level activated (Only changes during the low levels will change waveform)

Name the 4 parts of a pulse.

High trigger level, low trigger level, positive leading edge, negative trailing edge.

How do you determine if an output will be positive or negative edged?

If the dynamic input indicator (triangle in clock position) is high activated (+) or low activated with a not (-).

What happens in a Flip-Flop if the Clock is Low?

In any flip-flop if the clock is low it acts as a NO CHANGE and holds the output in whatever state it was previously in. *Except in the event of a preset or clear overriding the other inputs

What is meant by not symbols or lines over the Preset and Clear in a flip-flop?

It is low activated and will not override the other input signals unless activated by a low preset or clear pulse. (The lack of a not or line over the preset or clear means they are high activated)

In a JK Flip-Flop if Pre/Clr are not active what happens when J/K are both LOW? HIGH?

J LOW, K LOW = No Change J HIGH, K HIGH = Toggle

If an IC has 112 gates it is classified?

Large Scale Integration (LSI) 100 - 9,999 SSI: 0-11 MSI: 12 - 99 VLSI: 10,000 - 99,999 ULSI: 100,000+

Difference between latches and flip-flops?

Latches change states with input changes, flip-flops change states when a clock pulse is changed

The pin indicator on an IC indicates the number _____ pin?

Number 1 pin and the pins are then labelled in a counter clockwise direction from the 1 pin.

What happens when comparator 2 drops below 1/3 Vcc?

Output goes HIGH when trigger voltage goes below 1/3

What happens when comparator 1 uses more than 2/3 Vcc?

Output goes LOW when threshold voltage goes above 2/3

Preset cause the output to go to what state? Clears?

Preset - Sets the output Clear - Resets the output

What is the result of R - 1, S - 0? R-0, S-1?

R-1, S-0 = Reset (Easily remembered by R for "reset") R-0, S-1 - Set

Explain a Set state and Reset state in a D-Type Flip Flop.

Set - D is HIGH, C is HIGH Reset - D is LOW, C is HIGH

If Pre/Clr are not active in a J/K describe the inputs that would result in a SET state? RESET state?

Set - J is HIGH, K is LOW Reset - J is LOW, K is HIGH

Describe a SET state? RESET?

Set - Q is HIGH, Q not is LOW Set - Q is LOW, Q not is HIGH

What are the 4 logic families?

TTL - transistor transistor logic 0 - 5 Volts CMOS - 0 - 15 Volts ECL - speediest switcher ILL - Analog and digital interaction

Purpose of a flip-flop?

To store the last input condition until the next input condition is applied.

What is meant by toggle? What is the only flip-flop that uses toggle?

Toggle occurs in a JK Flip-Flop when both inputs are HIGH. The output switches states following a toggle.

True/False: Flip-flops store information by using feedback from output gates to input gates?

True

What is a universal logic gate?

Universal Logic gates can produce the logic functions of other gates by the way they are connected.

In a Clocked RS Flip-Flop how does the Clock effect the Flip-Flop?

When the Clock is HIGH it functions in the same way a RS Flip-Flop does. When the Clock is LOW it acts as a No Change remaining in whatever state it was previously in.

Purpose of a 555 timer

to provide digital timing